Patents by Inventor Michael Azevedo

Michael Azevedo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060010354
    Abstract: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.
    Type: Application
    Filed: July 12, 2004
    Publication date: January 12, 2006
    Inventors: Michael Azevedo, Carol Spanel, Andrew Walls
  • Publication number: 20050240833
    Abstract: A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation of the initial data tag set. The data transfer commands are issued with the attached data tags from the designated data tag set until an occurrence of a reset error associated with one of the issued data transfer commands. In response to the reset error, the data initiator device designates a different data tag set for tagging data transfers to thereby attach data tags from the newly designated data tag set to commands directed to data transfers between the data initiator device and the data target device subsequent to the designation of the new data tag set.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 27, 2005
    Applicant: International Business Machines Corporation
    Inventors: Michael Azevedo, Carol Spanel, Andrew Walls
  • Publication number: 20050229019
    Abstract: A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.
    Type: Application
    Filed: March 23, 2004
    Publication date: October 13, 2005
    Inventors: Michael Azevedo, Hugh McDevitt, Carol Spanel, Andrew Walls