Abstract: Provided herein are RET kinase inhibitors according to the formula: pharmaceutically acceptable salts thereof, pharmaceutical compositions thereof, and methods for their use in the treatment of diseases that can be treated with a RET kinase inhibitor, including RET-associated diseases and disorders. A, R1, n, X1, X2, X3, X4, and R2 have the meanings given in the specification.

Abstract: Systems and methods are provided for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering and/or sending each lead to the best available agent or agents.

Abstract: Systems and methods are provided for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering and/or sending each lead to the best available agent or agents.

Abstract: Systems and methods are provided for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering and/or sending each lead to the best available agent or agents.

Abstract: The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering or sending each lead to the best available agent or agents.

Abstract: The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering or sending each lead to the best available agent or agents.

Abstract: The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering or sending each lead to the best available agent or agents.

Abstract: The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering or sending each lead to the best available agent or agents.

Abstract: The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering and/or sending each lead to the best available agent or agents.

Abstract: A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage.

Abstract: A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage.

Abstract: A first and a second group of individual transistors in a voltage reference may collectively function as a first and a second composite transistor with a first and a second emitter area equal to the combined areas of the emitters of the first and the second groups of individual transistors, respectively. The second emitter area may be larger than the first emitter area. The stability of the reference voltage may depend upon the stability of the ratio between the first emitter area and the second emitter area. The first group of individual transistors may not be at the center of an arrangement of the second group of individual transistors. The constant reference voltage may vary due to thermal hysteresis by less than 200 parts per million over a 40 degree centigrade temperature range.

Abstract: The present invention is directed to a system and method for generating, processing and distributing leads, the system comprising a leads processing engine for receiving customer requests, creating leads based upon the customer requests, determining a best available agent or agents for each lead from a pool of available agents based upon one or more selected factors, and offering and/or sending each lead to the best available agent or agents.

Abstract: A bandgap voltage reference circuit having temperature curvature correction, comprises a bandgap voltage source configured to generate an output voltage, and a novel curvature correction circuit. The correction circuit is responsive to the bandgap voltage source output voltage and connected to apply a curvature correction signal to the bandgap voltage source to compensate for output voltage temperature dependency of the bandgap voltage source.

Abstract: A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.

Abstract: A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Abstract: The present invention provides a digital clock recovery circuit, which includes a frequency synthesizer generating a number of clock phase signals. The digital clock recovery circuit also includes a phase interpolation unit, which interpolates the clock phase signals from the frequency synthesizer to increase the number of clock phase signals. Additionally, the digital clock recovery circuit also includes a phase detector, a digital filter, and a phase selection unit. The phase detector has an output connected to a digital filter, which is connected to the phase selection unit. The phase detector sends signals filtered through the digital filter to select clock phase signals input into the phase selection unit from the phase interpolation unit. The output of the phase selector provides the recovered clock signal and also connected to the input phase detector.

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Abstract: A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.