Abstract: A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable.

Abstract: A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing circuit includes a transistor with only its bulk terminal connected to the substrate; the source, gate, and drain of this sensing transistor are not connected to the substrate. A differential comparator compares the output of the sensing transistor to the programmable reference voltage and enables the oscillator when the sensing transistor output is lower than the reference voltage.