Abstract: The various implementations described herein include methods, devices, and systems for automatic audio equalization. In one aspect, a method is performed at an audio device having one or more processors, memory, and a plurality of device interface elements, including one or more speakers and a plurality of microphones. The method includes: (1) detecting a change in orientation of the audio device from a first orientation to a second orientation; and (2) in response to detecting the change in orientation, configuring operation of two or more of the plurality of device interface elements.

Abstract: The various implementations described herein include methods, devices, and systems for automatic audio equalization. In one aspect, a method is performed at an audio device having one or more processors, memory, and a plurality of device interface elements, including one or more speakers and a plurality of microphones. The method includes: (1) detecting a change in orientation of the audio device from a first orientation to a second orientation; and (2) in response to detecting the change in orientation, configuring operation of two or more of the plurality of device interface elements.

Abstract: The apparatus described is a multi-core processor 505 adapted to provide digital to analog conversion. At least one 2010 of the cores 510 is used to make the conversion, another group of cores 2005 can provide the source of a digital stream of information such as audio visual signals. The stream is conveyed to processor 2010 optionally by a transfer processor 2015. The method of the invention divides each word of an incoming digital stream of information into a most significant and least significant portions. The most and least significant portions control the production of electrical charges which are added together to produce an analog electrical signal proportional to the values of the words in the digital stream.

Abstract: A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors 305(da), which splits off a substream and passes the data stream onto a second processor 305(db), which repeats the process; this continues until all of the data stream has been split into substreams. Each substream is processed in parallel by a second grouping 315 of processors. This second group of processors may have multiple steps and processors 315, 320. The processed substreams are assembled into a single data stream 330 by a third group of processors 325 reversing the splitting process and outputted from the array by a last processor 305(ae).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory.

Abstract: A system for pseudorandom number generation. A processor is provided that has a first memory to hold a first value and a second memory to hold a second value. Then a logic performs a +* operation while a looping condition is true.

Abstract: The apparatus described is a multi-core processor 505 adapted to provide digital to analog conversion. At least one 2010 of the cores 510 is used to make the conversion, another group of cores 2005 can provide the source of a digital stream of information such as audio visual signals. The stream is conveyed to processor 2010 optionally by a transfer processor 2015. The method of the invention divides each word of an incoming digital stream of information into a most significant and least significant portions. The most and least significant portions control the production of electrical charges which are added together to produce an analog electrical signal proportional to the values of the words in the digital stream.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a crawler (201) which is capable of traversing multiple processors along a predefined path (202) and performing a series of operations in preselected computers.

Abstract: A series of computers to process data including a first and a last computer. Each of the computers except the first is preceded by a prior computer and each except the last is followed by a subsequent computer. A logic reads new data via a first data path and a logic writes old data via a second data path. A logic process the new data to produce the old data and, except for the last computer, a storage element stores the old data. The logic to write operates after the logic to read and the logic to write operates before the logic to process.

Abstract: A process for loading a signal data values and convolution filter coefficient values into a target processor (ct) in a set of processors (cutil) utilized to calculate a convolution. The coefficient values are mapped to cutil. An interleave of the data values and of the coefficient values determined for ct. The coefficient values are loaded in ct and the data values are loaded in ct, thereby preparing ct to participate in calculating the convolution.

Abstract: A system for calculating a convolution of a data function with a filter function utilizing an array of processors including first and last processors. A coefficient value based on a derivation of the filter function and a data value representative of the data function are multiplied to produce a current intermediate value. Except in the first processor, a prior intermediate value is then added to the current intermediate value. Except in the last processor, the data and current intermediate values are then sent to the next processor. Then the last processor's prior intermediate value, if any, is added to its current intermediate value to produce a result value, wherein the result values collectively are representative of the convolution of the data function with the filter function.