Abstract: This invention relates to an efficient way to calibrate and control a raster output scanner (ROS). The scan non-linearity of a ROS may be measured and an appropriate calibration curve setting for the ROS may be determined. The setting and other scan line parameters may then be used as an address to a memory, such as a read-only memory (ROM). The memory may store a set of calibration curve data and the address is used to look up the data from one of these curves. The ROS may then be controlled based on the calibration data retrieved from memory.

Abstract: A signal synchronizer according to embodiments herein uses a delay register that receives a feedback signal. The delay register has many delay circuits, each of which are adapted to delay the feedback signal at different time intervals. A storage register made up of many binary storage devices receives a reference signal. Each storage device is adapted to store a feedback signal state of a corresponding delay circuit. As the feedback signal is delayed the additional time intervals by the successive delay circuits, it will change states (either from high to low, or low to high) and the different storage devices simultaneously store the feedback signal states of each of the delay circuits, as controlled by the reference signal. The change in feedback signal state between adjacent storage devices records a synchronization separation between the feedback signal and the reference signal. A control device synchronizes the feedback signal based on the synchronization separation as recorded by the storage register.

Abstract: A method for calibrating a VCO within a phase locked loop circuit is disclosed. First, a DAC output voltage is set to its minimum, and a counter M is adjusted until a comparator is its threshold voltage. Next, the DAC is set to another voltage, and counter M is again adjusted to the comparator threshold. This process is repeated for as many steps as desired. When the phase locked loop circuit requests an instantaneous frequency, an interpolation of the requested frequency against the curve created by the above-described method gives the value required by the DAC.

Abstract: A system architecture for scanned non-linearity correction in a printer uses any raster output scanner having scanned non-linearity profile previously stored in memory from a test station installed with any pixel board. The pixel board includes a correction table register wherein the pixel board utilizes the scanned non-linearity profile of the raster output scanner to calculate the correction table register to correct for pixel misregistration.

Abstract: A system architecture for scanned non-linearity correction in a printer uses any raster output scanner having scanned non-linearity profile previously stored in memory from a test station installed with any pixel board. The pixel board includes a correction table register wherein the pixel board utilizes the scanned non-linearity profile of the raster output scanner to calculate the correction table register to correct for pixel misregistration.

Abstract: An integrated information support system (IISS) uses a stand-alone, large capacity memory device, such as a CD ROM, to enhance the user interface of a copier system. The IISS, providing system users with access to vast quantities of graphical, textual, video and audio information, is a separately controlled system which may be integrated with the normal control functions of the copier system. Information is retrieved from the memory device and presented to a system user either spontaneously, on-demand, or in response to specific system conditions such as faults. In a preferred embodiment, an expert coach controls the presentation of information and is capable of monitoring user actions to, for example, ensure a suggested course of action is actually being followed. The IISS may advantageously share existing user interface facilities, such as the copier system's video monitor and button matrix.

Abstract: A method for calibrating a VCO within a phase locked loop circuit is disclosed. First, a DAC output voltage is set to its minimum, and a counter M is adjusted until a comparator is its threshold voltage. Next, the DAC is set to another voltage, and counter M is again adjusted to the comparator threshold. This process is repeated for as many steps as desired. When the phase locked loop circuit requests an instantaneous frequency, an interpolation of the requested frequency against the curve created by the above-described method gives the value required by the DAC.

Abstract: A method for calibrating a VCO within a phase locked loop circuit is disclosed. First, a DAC output voltage is set to its minimum, and a counter M is adjusted until a comparator is its threshold voltage. Next, the DAC is set to another voltage, and counter M is again adjusted to the comparator threshold. This process is repeated for as many steps as desired. When the phase locked loop circuit requests an instantaneous frequency, an interpolation of the requested frequency against the curve created by the above-described method gives the value required by the DAC.

Abstract: A digital phase detector utilizes a digital compartor and a plurality of delay elements. The comparator compares two signals and generates an output signal with a duration corresponding to the time delay between the arrival times of two signals. The output signal propagates through the plurality of delay elements. The number of delay elements that cover the duration of the output signal determine a time value for the duration of the output signal.

Abstract: A reference frequency and facet to facet correction circuit utilizes a phase locked loop which includes a digital phase detector to measure the time difference between the end of scan and the end of count of each facet and store them in a lookup table. The phase locked loop continuously generates an average time value form the time differences of all the facets of the polygon. The phase locked loop also adds the errors of each facet to the average time value and uses the result to correct the frequency of a pixel clock generator for both the reference frequency and facet to facet errors.

Abstract: A current regulator is disclosed which utilizes a well known driver chip. The driver chip has an input signal known as a brake signal "BRK" which typically is used to stop a standard DC motor. In this invention, the brake signal "BRK" is used to create a low resistance current path in order to sustain the current of the current regulator which is used in conjunction with a stepper motor.