Patents by Inventor Michael B. Roth

Michael B. Roth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for characterizing a delay locked loop
    Patent number: 7068085
    Abstract: A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 27, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Tyler J. Gomm, Michael B. Roth
  • Method and apparatus for characterizing a delay locked loop
    Publication number: 20040232962
    Abstract: A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Inventors: Tyler J. Gomm, Michael B. Roth
  • Method and apparatus for characterizing a delay locked loop
    Patent number: 6774687
    Abstract: A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tyler J. Gomm, Michael B. Roth
  • Method and apparatus for characterizing a delay locked loop
    Publication number: 20030169084
    Abstract: A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 11, 2003
    Inventors: Tyler J. Gomm, Michael B. Roth