Patents by Inventor Michael B. Solka
Michael B. Solka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180267846Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Patent number: 10007806Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: GrantFiled: April 14, 2016Date of Patent: June 26, 2018Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Patent number: 9990241Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: GrantFiled: June 23, 2017Date of Patent: June 5, 2018Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Publication number: 20170286196Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: ApplicationFiled: June 23, 2017Publication date: October 5, 2017Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Patent number: 9720867Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: GrantFiled: July 25, 2016Date of Patent: August 1, 2017Assignee: COHERENT LOGIX, INCORPORATEDInventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Patent number: 9558150Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.Type: GrantFiled: March 17, 2016Date of Patent: January 31, 2017Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Afzal M. Malik, Kenneth R. Faulkner, Michael B. Solka
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Publication number: 20160335218Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Publication number: 20160328231Abstract: In some embodiments, an apparatus includes processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus. In some embodiments the apparatus includes front-end circuitry configured to retrieve a plurality of instructions for execution and, based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. In some embodiments, this may reduce power consumption by the apparatus.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 9442461Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.Type: GrantFiled: August 17, 2015Date of Patent: September 13, 2016Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Jan D. Garmany, Michael B. Solka, Martin A. Hunt
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Patent number: 9430369Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.Type: GrantFiled: May 23, 2014Date of Patent: August 30, 2016Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 9430422Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.Type: GrantFiled: March 27, 2013Date of Patent: August 30, 2016Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
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Patent number: 9424441Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: GrantFiled: October 2, 2014Date of Patent: August 23, 2016Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Publication number: 20160232357Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Publication number: 20160196234Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.Type: ApplicationFiled: March 17, 2016Publication date: July 7, 2016Inventors: Carl S. Dobbs, Afzal M. Malik, Kenneth R. Faulkner, Michael B. Solka
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Patent number: 9323714Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.Type: GrantFiled: October 10, 2013Date of Patent: April 26, 2016Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Afzal M. Malik, Kenneth R. Faulkner, Michael B. Solka
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Publication number: 20150355596Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Michael B. Doerr, Jan D. Garmany, Michael B. Solka, Martin A. Hunt
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Patent number: 9134698Abstract: System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.Type: GrantFiled: August 20, 2012Date of Patent: September 15, 2015Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Jan D. Garmany, Michael B. Solka, Martin A. Hunt
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Publication number: 20150026451Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: ApplicationFiled: October 2, 2014Publication date: January 22, 2015Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
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Publication number: 20140351551Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.Type: ApplicationFiled: May 23, 2014Publication date: November 27, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
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Patent number: 8880866Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.Type: GrantFiled: October 14, 2011Date of Patent: November 4, 2014Assignee: Coherent Logix, IncorporatedInventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson