Abstract: A method includes modifying, at a bit error injection circuit, a multiplier value by a first value according to an occurrence of a first event. The method also includes, in response to a determination that the modified multiplier value matches a first threshold, modifying, at the bit error injection circuit, the offset value according to an occurrence of a second event. The method further includes, in response to a determination that the modified offset value matches a second threshold, asserting, at the bit error injection circuit, an error injection signal. The method further includes asserting a first error pattern to be transmitted via a bus lane based on the error injection signal.

Abstract: A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.

Abstract: A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N<NMAX, lines not carrying functional data are partially powered down between calibrations.

Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.

Abstract: A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.

Abstract: A parallel data link includes a redundant line. The redundant line permits one line to be calibrated while the others carry functional data, a switching mechanism enabling each line to be selected in turn for calibration. Control information for controlling the link, which is preferably for coordinating calibration activity, is communicated on the line selected for calibration. Preferably, the link is bi-directional, having a separate redundant line in each direction, enabling a bi-directional handshaking protocol to be used for communicating control information. Preferably, the lines selected for calibration are time-multiplexed to carry calibration patterns and control information at different time intervals.

Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Abstract: In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.