Abstract: This disclosure relates to fault tolerant instantiations of a cardiac therapy delivery device such as an implantable cardiac stimulator (e.g., an implantable pulse generator, IPG, and/or an implantable cardioverter-defibrillator, ICD) coupled to an implantable physiologic sensor (IPS). According to the disclosure delivery of cardiac pacing and/or cardioversion-defibrillator therapy delivery can cause errors in output signals from an IPS. Resolution of such errors involves selectively energizing (or disconnecting the output signal from) the IPS during pacing and/or defibrillation therapy delivery. Programmable signal “blanking” in lieu of or in addition to the foregoing also improves the integrity of the output signal (i.e., continuously energize the IPS and ignore parts of the output signal). An ICD having a transient weakness in an insulated conductor used for the IPS signal can likewise have the IPS de-energized and/or blank the IPS output signal during high voltage therapy delivery.

Abstract: This disclosure is directed to the synchronization of clocks of a secondary implantable medical device (IMD) to a clock of a primary IMD. The secondary IMD includes a communications clock. The communications clock may be synchronized based on at least one received communications pulse. The secondary IMD further includes a general purpose clock different than the communications clock. The general purpose clock may be synchronized based on at least one received power pulse. The communications clock may also be synchronized based on the at least one received power pulse.

Abstract: In general, this disclosure describes techniques for reducing power consumption within an implantable medical device (IMD). An IMD implanted within a patient may have finite power resources that are intended to last several years. To promote device longevity, sensing and therapy circuits of the IMD are designed to incorporate an analog-to-digital converter (ADC) that provides relatively high resolution output at a relatively low operation frequency, and does so with relatively low power consumption. An ADC designed in accordance with the techniques described herein utilizes a quantizer that has a lower resolution than a digital-to-analog converter (DAC) used for negative feedback. Such a configuration provides the benefits of higher resolution DAC feedback without having the use high oversampling ratios that result in high power consumption. Also, the techniques avoid the use of, and the associated high power consumption of, a high resolution flash ADC, within the sigma delta loop.

Abstract: In general, this disclosure describes techniques for reducing power consumption within an implantable medical device (IMD). An IMD implanted within a patient may have finite power resources that are intended to last several years. To promote device longevity, sensing and therapy circuits of the IMD are designed to incorporate an analog-to-digital converter (ADC) that provides relatively high resolution output at a relatively low operation frequency, and does so with relatively low power consumption. An ADC designed in accordance with the techniques described herein utilizes a quantizer that has a lower resolution than a digital-to-analog converter (DAC) used for negative feedback. Such a configuration provides the benefits of higher resolution DAC feedback without having the use high oversampling ratios that result in high power consumption. Also, the techniques avoid the use of, and the associated high power consumption of, a high resolution flash ADC, within the sigma delta loop.

Abstract: The present invention provides a method and apparatus for detecting magnetic fields in implantable medical devices. The apparatus includes a sensor adapted to provide at least one signal proportional to at least one vector component of a magnetic field. The apparatus further includes a circuit adapted to receive the signal and perform a predetermined action when a predetermined quantity exceeds a predetermined threshold value.

Abstract: The present invention provides a method and apparatus for detecting magnetic fields in implantable medical devices. The apparatus includes a sensor adapted to provide at least one signal proportional to at least one vector component of a magnetic field. The apparatus further includes a circuit adapted to receive the signal and perform a predetermined action when a predetermined quantity exceeds a predetermined threshold value.

Abstract: Multi-chamber cardiac pacing systems for providing multi-site pacing to at least one of the right and left atria and then synchronously to the right and left ventricles in a triggered pacing sequence while providing for recharge of the output capacitors of each output amplifier in the shortest time. The recharge operations of the present invention come into play when bi-chamber pacing is invoked to deliver right and left heart chamber pacing pulses that are separated by a triggered pacing delay that overlaps, i.e., is shorter than, the recharge time period. In a truncated recharge mode, the first pacing pulse is delivered through the first pacing path, and the recharging of the first pacing path is commenced for the duration of the triggered pacing delay. Then, the second pacing pulse is delivered, and the second pacing path is recharged for a second recharge period. The recharging of the first pacing path is conducted simultaneously with or after completion of the second recharge period.

Abstract: A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input terminal (16) of the voltage comparator circuit (12) for generating a reference voltage. A delay circuit (50, 52) is coupled to an output terminal (42) of the voltage comparator circuit (12). A discharge device (54) is coupled to the delay circuit (50, 52) and to the capacitor (20) for discharging the capacitor (20). A switching device (40) is coupled to the output (42) of the voltage comparator circuit (12) and to the resistor divider network (30) for controlling the application of the reference voltage to voltage comparator circuit (12).

Abstract: A compensation circuit (10) controls the gain of transmit and receive amplifiers (47), (49) as a function of a residual input current (I.sub.res). Circuit (10) includes a constant current source (24) which is connected to produce mirrored constant currents in transistors (26) and (28). The residual current is passed through a resistor (R.sub.loop) to produce a reference voltage. The constant current from the transistor (26) is divided with the first part of the current passing through the resistor (R.sub.loop) and the second part of the current passing through a resistor (50) and a transistor (54). The transistor (54) is connected in a mirror configuration with a transistor (58). When the residual current increases, the current mirrored to transistor (58) decreases. A transistor (32) is connected in parallel with the transistor (58) to receive the remaining current from the transistor (28) which is not drawn by the transistor (58).

Abstract: A sidetone circuit (44) is connected to the terminals of a two-line telephone system. The sidetone circuit (44) receives inputs from a DTMF source (62) and a microphone (72). These inputs are selectively passed through a circuit (82) to produce a modulating signal which controls a current source (46) and a current (54). The current source (46) is connected between the telephone line terminals. The input audio signal from the microphone (72) modulates the current source (46) to impress a voltage upon the telephone line. The current source (54) is connected between a first of the telephone lines and a balance node (60). A resistor (58) is connected between the balance node and the second of the telephone lines. An incoming audio signal over the telephone line is coupled to the balance node (60) for summing with an inverted audio signal. The input audio signal from the microphone (72) is further coupled to the balance node (60).

Abstract: A low loop current switch latch circuit (10) monitors a residual current which is derived from a telephone line and is proportional to the current drawn by a telephone subscriber circuit. Bipolar transistors (20, 26) are connected to produce a proportional current to the residual current. A current mirror circuit includes a master transistor (30) and a slave transistor (32). The proportional current is drawn through the master transistor (30). The current produced by the slave transistor (32) is provided to a node (33). A constant power source (36) provides a constant current to a node (39). A pair of cross-coupled transistors (40, 46) are connected to the nodes (33, 39) such that the cross-coupled transistors are set to first and second states as a function of the current derived from the slave transistor (32).

Abstract: A current supplementation circuit is designed to operate in conjunction with a two-terminal telephone line for supplying additional current to the output of a voltage regulator (42). A nonregulated voltage is received at first and second terminals (18, 20) with the nonregulated voltage comprising both DC and AC signals. An essentially regulated voltage is produced at a terminal (12) at the output of the voltage regulator (42). An essentially constant current is drawn from the first terminal (41) and provided to the second terminal (20) to provide an indication that the subscriber circuit is active. This constant current comprises first and second partial currents. The first partial current is passed through a control transistor (98) through a parasitic collector to the second terminal (14). The second partial current is passed through the control transistor (98) to the regulated voltage terminal (12) when the voltage at this terminal drops.

Abstract: A circuit (10) is provided for use in a telecommunications integrated circuit which has a memory for storing a telephone number. The circuit (10) essentially comprises a latch having differential nodes (22, 28). The circuit (10) serves to detect when the supply voltage provided between the supply terminals (12, 14) drops to a level which causes loss of the data stored in the integrated circuit memory. An output signal (PUC) is driven to a low state upon detection of loss of power. For a slow return of supply power the nodes (22, 28) are respectively pulled to low and high states by current leakage through diodes (30, 36, 38) connected to the power terminals (12, 14). For a rapid supply voltage transition the latch node (28) is pulled high by capacitive coupling through a diode (30). This serves to set the latch in the condition where the output node (22) is at a low state to indicate loss of power. After generation of the PUC signal in the low state, external circuitry provides a reset signal (.phi..sub.

Abstract: A voltage reference circuit (10) produces a reference voltage at output terminals (66, 76). The output reference voltage is substantially independent of variations in the supply voltage, integrated circuit manufacturing processes and temperature. A current reference circuit (30, 32, 34, 36, 38, 56 and 84) produces constant emitter currents in bipolar transistors (40, 70). The V.sub.BE of the bipolar transistors (40, 70) is a stable reference due to the constant emitter current. The bipolar transistors (40, 70) are manufactured with similar geometries to eliminate dependence of the reference voltage upon bipolar processing variations. The V.sub.BE of the bipolar transistor (40) produces a reference current which is provided to the base terminal of bipolar transistor (70). The V.sub.BE of bipolar transistor (70) is further utilized to produce the output reference voltage.