Abstract: Electronic device packages that allow batteries to be incorporated in the package directly above or below semiconductor die or other devices can enable reduced package footprints while also protecting batteries against exposure to undesirable high temperatures during assembly of the package and protecting molded portions of the package from stresses that may arise from swelling of the battery over its useful lifetime. One terminal of the battery is bonded a conductive lead integrated within a molded cover by an electrically conductive bond. Bonding the cover to a circuit board or other substrate also electrically couples to battery terminal to a contact on the substrate. The other terminal of the batter can be bonded to another contact on the substrate using a suitable conductive bond such as one formed by an electrically conductive adhesive.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a conductive die connector having a first end connected to a die pad of a semiconductor die. A first encapsulant formulated for selective activation by way of a laser encapsulates at least a portion of the semiconductor die. A first conductive trace of a redistribution layer is formed by plating a conductive material on a first laser activated path on a first major surface of the first encapsulant. The first conductive trace is directly connected to a second end of the die connector. A second encapsulant formulated for selective activation by way of a laser encapsulates at least the first conductive trace and exposed portions of the first major surface of the first encapsulant.

Abstract: A package is formed that encapsulates first and second components having respective first and second thickness differing from each other. Each component has lower surface provided with electrical contact pads and an upper surface opposite the lower surface. A volume of molding material encapsulates the first component. The package includes a set redistribution layers including a set of electrically-conductive interconnects surrounded by electrically-insulating material. The redistribution layers are disposed above the upper surface of the first component. The package includes one or more electrically conductive interconnects that pass through the redistribution layers to the lower surface of the first component. The second component is disposed at a location adjacent to the first component. A first portion of the second component is surrounded by the volume of molding material and a second portion of the second component is surrounded by one or more of the redistribution layers.

Abstract: A system and method provides a substrate having a first surface and a second surface. A first plurality of contact pads are formed on the first surface of the substrate. A first redistribution layer is formed over the first surface of the substrate by mounting a plurality of metal balls to contact pads of the first plurality of contact pads on the first surface of the substrate, wherein the plurality of metal balls include copper, forming a layer of encapsulant surrounding at least a portion of the plurality of metal balls, depositing a dielectric layer over the plurality of metal balls and the encapsulant, and forming a second plurality of contact pads over the dielectric layer, wherein each contact pad of the second plurality of contact pads is connected through openings in the dielectric layer to metal balls of the plurality of metal balls.

Abstract: One or more integrated capacitors can be formed within the molding material(s) of a molded electronic device package. An electronic device such as a semiconductor die is surrounded by a first volume of molding material and a first capacitor plate is formed on a top surface of the first volume of molding material above the electronic device. A second volume of molding material is formed above the first capacitor plate and a second capacitor plate is formed on a top surface of the second volume of molding material which separates the second capacitor plate from the first capacitor plate.

Abstract: A semiconductor device package may include a package substrate, mold material formed over the package substrate, and a mold-embedded inductor that is embedded in the mold material. The mold-embedded inductor may be coupled to a die, such as a power management integrated circuit die, which may also be embedded in the mold material. The mold-embedded inductor may be formed by forming conductive traces and an inductor core in the mold material. For example, an active mold packaging (AMP) process and corresponding laser direct structuring (LDS) processes may be performed to form openings in the mold material and to activate surfaces of the mold material to facilitate subsequent plating of conductive material. Activated surfaces of the mold material may have micro-rough texture and may include bulk conductive material formed via the application of laser energy to additives in the mold material during the LDS process(es).

Abstract: A packaged device includes molding compound, a first semiconductor die disposed within the molding compound and a second semiconductor die disposed within the molding compound. The molding compound galvanically isolates the first and second semiconductor dies. The packaged device further includes communication coils constructed and arranged to provide communication between the first and second semiconductor dies through inductive coupling, at least one of the communication coils being fabricated within the molding compound.

Abstract: A multi-chip package includes two electronic components bonded to each other via electrical contacts on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that includes a upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more through-package interconnects that pass through the molding material. A first through-package interconnect couples an electrically conductive interconnect in a first redistribution layer to an electrically conductive interconnect in a second redistribution layer on an opposite side of the volume of molding material from the first redistribution layer, or it couples the interconnect to one of the components within the volume of molding material.

Abstract: A method of forming a semiconductor device is provided. The method includes encapsulating with an encapsulant at least a portion of a semiconductor die and a package substrate, the encapsulant including an additive selectively activated by way of a laser. A first opening is formed in the encapsulant, the first opening exposing a predetermined first portion of the package substrate. The additive is activated at the sidewalls of the first opening. A second opening is formed in the encapsulant, the second opening encircling the first opening and exposing a predetermined second portion of the package substrate. The additive is activated at the sidewalls the second opening. A conductive material is plated on the additive activated portions of the encapsulant.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a conductive die connector having a first end connected to a die pad of a semiconductor die. A first encapsulant formulated for selective activation by way of a laser encapsulates at least a portion of the semiconductor die. A first conductive trace of a redistribution layer is formed by plating a conductive material on a first laser activated path on a first major surface of the first encapsulant. The first conductive trace is directly connected to a second end of the die connector. A second encapsulant formulated for selective activation by way of a laser encapsulates at least the first conductive trace and exposed portions of the first major surface of the first encapsulant.

Abstract: A package is formed that encapsulates first and second components having respective first and second thickness differing from each other. Each component has lower surface provided with electrical contact pads and an upper surface opposite the lower surface. A volume of molding material encapsulates the first component. The package includes a set redistribution layers including a set of electrically-conductive interconnects surrounded by electrically-insulating material. The redistribution layers are disposed above the upper surface of the first component. The package includes one or more electrically conductive interconnects that pass through the redistribution layers to the lower surface of the first component; The second component is disposes at a location adjacent to the first component. A first portion of the second component is surrounded by the volume of molding material and a second portion of the second component is surrounded by one or more of the redistribution layers.

Abstract: A method of forming a self-aligned waveguide is provided. The method includes forming a first alignment feature on a packaged semiconductor device and a second alignment feature on a waveguide structure. A solder material is applied to the first alignment feature or the second alignment feature. The waveguide structure is placed onto the packaged semiconductor device such that the second alignment feature overlaps the first alignment feature. The solder material is reflowed to cause the waveguide structure to align with the packaged semiconductor device.

Abstract: An electronic device package and method of fabricating such a package includes a first and second components encapsulated in a volume of molding material. A surface of the first component is bonded to a surface of the second component. Upper and lower sets of redistribution lowers that include, respectively, first and second sets of conductive interconnects are formed on opposite sides of the molding material. A through-package interconnect passes through the volume of molding material and has ends that terminate, respectively, within the upper set of redistribution layers and within the lower set of redistribution layers.

Abstract: An antenna circuit may include a dielectric structure including a first surface; a second surface. and a plurality of laminae extending between the first surface and the second surface. Each lamina may include at least one thickness parameter, at least one slant parameter defining an angle between each lamina and one or more of the first surface or the second surface, and at least one pitch parameter defining an air gap between each lamina and one or more adjacent laminae. Each lamina is configured at least partially overlap the one or more adjacent laminae in a direction that is perpendicular to the first and second surfaces. The antenna circuit may include a first patch antenna disposed on the first surface. The dielectric structure may provide a selected effective permittivity for radio frequency signals from the first patch antenna in the direction that is perpendicular to the first and second surfaces.

Abstract: A multi-chip package includes two electronic components bonded to each other via features on corresponding faces of the components that are directly opposite each other. The components are encapsulated in a volume of molding material that can include upper and lower sets of redistribution layers disposed on upper and lower surfaces of the volume of molding material that include electrical interconnects. The package includes one or more internal interconnects that pass through an aperture in the first electronic component to electrically couple an electrical contact on a surface of the package to the second electronic component.

Abstract: A method of forming a package-on-package semiconductor device is provided. The method includes mounting an antenna sub-assembly on a first major side of a package substrate and a packaged RF semiconductor device on a second major side of the package substrate. The antenna sub-assembly includes an antenna substrate, an antenna substrate waveguide, and an antenna structure. The antenna substrate waveguide is aligned with a waveguide formed through the package substrate. The packaged RF semiconductor device includes a semiconductor die, an RDL formed over an active side of the first semiconductor die, and a signal launcher formed from a conductive layer of the RDL. The signal launcher is configured for propagation of an RF signal through the waveguide formed through the package substrate and the antenna substrate waveguide.

Abstract: A method of forming a semiconductor device is provided. The method includes interconnecting a semiconductor die and a flex substrate sub-assembly with a package substrate. The flex substrate sub-assembly includes a flexible conductive trace. A first portion of the flexible conductive trace is conductively connected to the package substrate. The method further includes encapsulating with an encapsulant at least a portion of the semiconductor die and the flex sub-assembly. A second portion of the flexible conductive trace is exposed at a top surface of the encapsulant.

Abstract: A semiconductor device package having a thermal dissipation feature is provided. The semiconductor device package includes a package substrate. A semiconductor die is mounted on a first surface of the package substrate. A thermal conductive structure including a die pad portion is affixed to the semiconductor die. A limb portion of the thermal conductive structure extends laterally away from the die pad portion and overlaps a portion of the package substrate. A thermal conduction path is formed between the semiconductor die and a distal end of the limb portion.

Abstract: A method of forming a self-aligned waveguide is provided. The method includes providing a radio frequency (RF) interposer. The RF interposer includes a non-conductive substrate, a radiating element formed on the non-conductive substrate, and a cavity formed in the non-conductive substrate. A packaged semiconductor die is affixed in the cavity of the RF interposer. A conductive material is dispensed to form a conductive path between a conductive connector of the packaged semiconductor die and the radiating element.

Abstract: An electronic device includes a device substrate with a mounting surface, an electronic circuit coupled to the mounting surface, and encapsulant material over the electronic circuit and the mounting surface. The encapsulant material has an upper encapsulant surface and a plurality of encapsulant sidewalls extending between the mounting surface of the device substrate and the upper encapsulant surface. The electronic device also includes a sidewall antenna coupled to one of the encapsulant sidewalls, and a shield structure embedded within the encapsulant material between the sidewall antenna and the electronic circuit. The sidewall antenna is electrically coupled to the electronic circuit through the device substrate. The shield structure extends from the mounting surface of the device substrate toward the upper surface of the encapsulant material. The sidewall antenna may be selected from an end-fire type of antenna and a broadside-fire type of antenna.