Abstract: In accordance with at least one embodiment, a first representation of a first gamma curve is stored in a look-up table, a second representation of a second gamma curve is stored in a look-up table, and a video signal is modified in accordance with an interpolation of at least a portion of the first representation of the first gamma curve and at least a portion of the second representation of the second gamma curve. In accordance with at least one embodiment, the at least a portion of the first representation of the first gamma curve is multiplied by a one's complement of a normalized weight factor, the at least a portion of the second representation of the second gamma curve is multiplied by the normalized weight factor, and the results are added together to obtain an output video signal.

Abstract: In accordance with at least one embodiment, a first representation of a first gamma curve is stored in a look-up table, a second representation of a second gamma curve is stored in a look-up table, and a video signal is modified in accordance with an interpolation of at least a portion of the first representation of the first gamma curve and at least a portion of the second representation of the second gamma curve. In accordance with at least one embodiment, the at least a portion of the first representation of the first gamma curve is multiplied by a one's complement of a normalized weight factor, the at least a portion of the second representation of the second gamma curve is multiplied by the normalized weight factor, and the results are added together to obtain an output video signal.

Abstract: A method and apparatus for correcting a video signal includes providing a comparison of correction data to safety margin data, and determining a level of correction based on this comparing, wherein video correction is provided, but clipping of the video signal is substantially prevented.

Abstract: A method of correcting a video signal includes retrieving a correction data from a respective one multiple memory devices; reordering the correction data to a predetermined order for a particular segment; and interpolating multiple correction data so that all pixels in the particular segment have a corresponding one of the correction data. An apparatus for correcting video comprises multiple memory devices, each having multiple correction data; a cross-bar switch that reorders at least some of the data to a predetermined order for a particular segment; and an interpolator that calculates multiple interpolated correction data. One of the correction data corresponds to one of multiple pixels in the segment.

Abstract: A block matching motion estimation algorithm uses reduced precision data when comparing pictures in the block to be compressed with pictures in a reference block. This yields a plurality of best match candidates. The average of the best match candidates, excluding those candidates which fall outside a predetermined cluster boundary, is determined and then a second search is performed focused on this average. In this way, the amount of hardware for the block matching algorithm is decreased and the speed of its operation is enhanced.

Abstract: A method of correcting a video signal includes retrieving a correction data from a respective one multiple memory devices; reordering the correction data to a predetermined order for a particular segment; and interpolating multiple correction data so that all pixels in the particular segment have a corresponding one of the correction data. An apparatus for correcting video comprises multiple memory devices, each having multiple correction data; a cross-bar switch that reorders at least some of the data to a predetermined order for a particular segment; and an interpolator that calculates multiple interpolated correction data. One of the correction data corresponds to one of multiple pixels in the segment.

Abstract: A contrast control and clipping device is configured to determine a maximum range of enhancement that may be applied to each pixel for picture sharpness enhancement. This maximum range is used to limit the enhancement that is determined by the conventional convolution kernel and gain control modules. Preferably, the maximum range is independent of the determined convolution value, thereby minimizing the bandwidth requirements among the modules used for picture sharpness enhancement. The reduced bandwidth requirement allows for an efficient partitioning of tasks between hardware and software embodiments, and eases the overall system design task. In a multi-media application, the amount of data that is transferred between the processor and sub-components is substantially reduced, and the efficient partitioning facilitates parallel processing.

Abstract: A method for motion coding an uncompressed digital video data stream such as an MPEG-2 digital video data stream. The method includes the steps of comparing pixels of a first pixel array in a picture currently being coded with pixels of a plurality of second pixel arrays in at least one reference picture and concurrently performing motion estimation for each of a plurality of different prediction modes in order to determine which of the prediction modes is an optimum prediction mode determining which of the second pixel arrays constitutes a best match with respect to the first pixel array for the optimum prediction mode, and, generating a motion vector for the first pixel array in response to the determining step. The method is implemented in a device such as a motion estimation search system of a digital video encoder.

Abstract: A method for motion coding an uncompressed digital video data stream such as an MPEG-2 digital video data stream. The method includes the steps of comparing pixels of a first pixel array in a picture currently being coded with pixels of a plurality of second pixel arrays in at least one reference picture and concurrently performing motion estimation for each of a plurality of different prediction modes in order to determine which of the prediction modes is an optimum prediction mode, determining which of the second pixel arrays constitutes a best match with respect to the first pixel array for the optimum prediction mode, and, generating a motion vector for the first pixel array in response to the determining step. The method is implemented in a device such as a motion estimation search system of a digital video encoder.

Abstract: A method for determining a best match between a first pixel array in a picture currently being encoded and a plurality of second pixel arrays in a search region of a reference picture, wherein each of the first and second pixel arrays includes a plurality of rows and columns of individual pixel values.

Abstract: A method for determining a best match between a first pixel array in a picture currently being encoded and a plurality of second pixel arrays in a search region of a reference picture, wherein each of the first and second pixel arrays includes a plurality R of rows and a plurality C of columns of individual pixel values.

Abstract: A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Abstract: A RAM-based search engine for updating a horizontal sum representing the sum of the values of N pixels contained in a horizontal row of a reference pixel array during a motion estimation search during which the reference pixel array is displaced by one pixel in a horizontal search direction during each of a plurality of iterations of the motion estimation search.

Abstract: A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Abstract: A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Abstract: A controller for controlling the operation of a variable length decoder, which includes a coding protocol determination circuit for determining a coding protocol used in coding a digital data stream currently being decoded by the variable length decoder, and a configuration control circuit for automatically reconfiguring the variable length decoder into a selected one of a plurality of different possible decoding configurations, depending upon the determined coding protocol. Also disclosed is a controller for controlling the operation of a variable length decoder, which includes a code type determination circuit which determines a code type of a current code word currently being decoded by the variable length decoder, and a mode switching circuit which switches a mode of operation of the controller between a parallel decoding mode of operation and a tree-searching mode of operation, depending upon the determined code type of the current code word.

Abstract: A variable length decoder for decoding an input digital data stream which includes a plurality of variable length code words which are coded in accordance with any of a plurality of different coding standards. The variable length decoder includes an input circuit which receives the input digital data stream and produces a decoding window that includes a leading word aligned bit stream, and a decoding circuit which is configurable into any selected one of a plurality of different decoding configurations, depending upon which coding standard the input digital data stream is coded in accordance with, the decoding circuit being coupled to the leading word aligned bit stream for decoding the length and value of each code word in the input digital data stream.

Abstract: A variable length decoder with adaptive acceleration in processing of an encoded input bit stream which includes an input section which receives the input bit stream and provides a decoding window that includes a sequence of bits which include one or more code words to be decoded at an output thereof. A code word length decoding section determines the combined length of a combination of two or more code words received from the input section in response to a first value of a control signal and generates a combined length signal representative of the determined combined length, and determines the length of an individual code word received from the input section in response to a second value of the control signal, and generates an individual code word length signal representative of the determined length of the individual code word.

Abstract: A microblock-level partitioned digital HDTV video decoder for decoding a bit stream consisting of a series of macroblocks of digital video data which are coded in accordance with an MPEG or other predetermined digital compression code. The decoder includes a bit stream parser for identifying boundaries between the macroblocks and producing macroblock boundary information indicative of the identified boundaries, a bit stream formatter for combining the macroblock boundary information with the bit stream to produce a combined bit stream having successive multi-bit portions, a rate buffer for storing and sequentially outputting the successive multi-bit portions, first and second FIFO memories, and a FIFO controller for alternately write enabling the first and second FIFO memories in response to the macroblock boundary information. The FIFO memories thereby alternately store the successive macroblocks in the combined bit stream sequentially outputted from the rate buffer.

Abstract: A variable length decoder (VLD) for processing an input bit stream (e.g., MPEG video) which includes qualifying and non-qualifying types of variable length code words. The VLD includes an input circuit for receiving the input bit stream and providing a sequence of available input bits, a shifter circuit for providing a decoding window that includes one or more code words contained in the sequence of available input bits, a code word length decoding circuit for determining whether or not the decoding window contains a pair of qualifying code words, and for determining the combined length of the pair of qualifying code words and producing a combined length signal representative of the determined combined length, if the decoding window contains a pair of qualifying code words, and further, for determining the length of a leading code word contained in the decoding window and producing a leading word length signal representative of the determined length of the leading code word.