Abstract: Techniques for autonomously tracking and/or predicting an alert event are provided. In one example, a system can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a schedule component that determines plan information for a hub of a plurality of hubs, and the hub can be coupled to a device. The computer executable components can further comprise a tracking component that identifies a deviation from the plan information by the hub. Additionally, the computer executable components can comprise a prediction component that determines a probability that the deviation will result in an alert event.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Techniques for autonomously tracking and/or predicting an alert event are provided. In one example, a system can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a schedule component that determines plan information for a hub of a plurality of hubs, and the hub can be coupled to a device. The computer executable components can further comprise a tracking component that identifies a deviation from the plan information by the hub. Additionally, the computer executable components can comprise a prediction component that determines a probability that the deviation will result in an alert event.

Abstract: Techniques for autonomously tracking and/or predicting an alert event are provided. In one example, a system can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a schedule component that determines plan information for a hub of a plurality of hubs, and the hub can be coupled to a device. The computer executable components can further comprise a tracking component that identifies a deviation from the plan information by the hub. Additionally, the computer executable components can comprise a prediction component that determines a probability that the deviation will result in an alert event.

Abstract: Techniques for autonomously tracking and/or predicting an alert event are provided. In one example, a system can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a schedule component that determines plan information for a hub of a plurality of hubs, and the hub can be coupled to a device. The computer executable components can further comprise a tracking component that identifies a deviation from the plan information by the hub. Additionally, the computer executable components can comprise a prediction component that determines a probability that the deviation will result in an alert event.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Techniques for autonomously tracking and/or predicting an alert event are provided. In one example, a system can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a schedule component that determines plan information for a hub of a plurality of hubs, and the hub can be coupled to a device. The computer executable components can further comprise a tracking component that identifies a deviation from the plan information by the hub. Additionally, the computer executable components can comprise a prediction component that determines a probability that the deviation will result in an alert event.

Abstract: Techniques for autonomously tracking and/or predicting an alert event are provided. In one example, a system can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory. The computer executable components can comprise a schedule component that determines plan information for a hub of a plurality of hubs, and the hub can be coupled to a device. The computer executable components can further comprise a tracking component that identifies a deviation from the plan information by the hub. Additionally, the computer executable components can comprise a prediction component that determines a probability that the deviation will result in an alert event.

Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.

Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.

Abstract: For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

Abstract: A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).

Abstract: For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

Abstract: Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.