Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

Abstract: In some implementations, a method of synchronizing a content generation and delivery architecture to reduce the latency associated with image passthrough. The method includes: determining a temporal offset associated with the content generation and delivery architecture to reduce a photon-to-photon latency across the content generation and delivery architecture; obtaining a first reference rate associated with a portion of the content generation and delivery architecture; generating, via synchronization circuitry, a synchronization signal for the content generation and delivery architecture based at least in part on the first reference rate; and operating the content generation and delivery architecture according to the synchronization signal and the temporal offset.

Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.

Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.

Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.

Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.

Abstract: Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).

Abstract: A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.

Abstract: A memory module includes a solid-state drive (SSD) and a memory controller. The memory controller receives information from a host memory controller via a synchronous memory channel and determines to initiate background tasks of the SSD based on memory commands and a state of the memory module. According to one embodiment, the synchronous memory channel is a DRAM memory channel, and the SSD includes a flash memory. The background tasks of the SSD such as garbage collection, wear leveling, and erase block preparation are initiated during an idle state of the memory module.

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).

Abstract: A system and a method select a datapath through a meshed Input/Output (IO) fabric. A plurality of port controllers is coupled to interconnection logic. Each port controller is coupled to a corresponding communication link and outputs a detection signal if the corresponding communication link transitions from a first lower-power state to a second higher power state. The interconnection logic, responsive to the detection signal, is configured to output a first signal to one or more selected port controllers to transition the corresponding communication link coupled to the selected port controller from the first power state to the second power state based on a frequency of use of a datapath between the communication link corresponding to the port controller outputting the detection signal and the communication link corresponding to each of the one or more selected port controllers.