Patents by Inventor Michael Bekerman
Michael Bekerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250104742Abstract: Adjustable clock and power gating control is facilitated hereby. In aspects, a power management circuit is coupled to a memory controller circuit that is coupled to a memory resource circuit and to a plurality of heterogeneous client circuits configured to access the memory resource circuit via the memory controller circuit. The power management circuit is configured to receive operating parameters associated with the plurality of client circuits and to determine, based on the operating parameters, a threshold power state for the memory resource circuit. Additionally, the power management circuit is configured to initiate a clock gating operation, a power gating operation, or both for the memory resource circuit and to maintain at least the threshold power state for the memory resource circuit by limiting performance of the clock gating operation, the power gating operation, or both for the memory resource circuit. Other aspects and features are also claimed and described.Type: ApplicationFiled: June 28, 2024Publication date: March 27, 2025Inventors: Michael Bekerman, Matthew R. Johnson, Lior Zimet, Rohit K. Gupta
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Publication number: 20250093925Abstract: An apparatus includes a control circuit, configured to transition a plurality of power domains into selected performance states, and a set of state request registers. A state request register may include fields that are associated with respective power domains. The apparatus may further include circuit blocks configured to store respective state request values into respective state request registers. A given state request value may indicate a requested performance state for at least one of the power domains. In addition, a performance management circuit may be configured to select, using the associated fields in the registers, a particular performance state for at least one of the power domains. The performance management circuit may be further configured to determine a transition path to sequence to the selected performance state, and to cause the control circuit to transition to the selected performance state using the transition path.Type: ApplicationFiled: December 14, 2023Publication date: March 20, 2025Inventors: Doron Rajwan, John H. Kelm, Josh P. de Cesare, Karl D. Wulcan, Michael Bekerman
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Publication number: 20250093937Abstract: A system includes a power management processor that may be configured to monitor operation of one or more circuit blocks in the system, and to determine a particular performance state of a set of performance states for one or more power domains in the system based on the monitored operation. The system further includes a performance management circuit that may be configured to receive, from the power management processor, an indication of the particular performance state. The performance management circuit may further be configured to determine a transition path from a current performance state to the particular performance state that avoids illegal performance state transitions, and to cause a control circuit to transition to the particular performance state using the transition path.Type: ApplicationFiled: December 14, 2023Publication date: March 20, 2025Inventors: Doron Rajwan, John H. Kelm, Michael Bekerman
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Patent number: 12212729Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.Type: GrantFiled: August 8, 2023Date of Patent: January 28, 2025Assignee: Apple Inc.Inventors: Yung-Chin Chen, Michael Bekerman, Guy Côté, Aleksandr M. Movshovich, D. Amnon Silverstein, David R. Pope
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Publication number: 20240372692Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: ApplicationFiled: May 28, 2024Publication date: November 7, 2024Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Patent number: 12111721Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.Type: GrantFiled: October 19, 2023Date of Patent: October 8, 2024Assignee: Apple Inc.Inventors: Marc A. Schaub, Roy G. Moss, Michael Bekerman
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Publication number: 20240320776Abstract: Embodiments relate to generating a Quality of Service (QOS) parameter indicating latency tolerance of an image signal processor by determining and processing latency tolerance values of its individual pipeline circuits. At least a subset of the pipeline circuits that performs image processing functions generates their individual latency tolerance values. Each of the individual latency tolerance value is determined as a difference between a sampling time at which an operation is performed on certain pixel data and a latest time by which the operation should be performed on the same pixel data. The individual latency tolerance values generated in this manner provides a mechanism to determine the QoS parameter relevant to an image signal processing scheme that involves access to memory multiple times to save and retrieve intermediate pixel data and process incoming pixel data in a real-time manner.Type: ApplicationFiled: March 22, 2023Publication date: September 26, 2024Inventors: Hoi Man S. Ng, Oren Kerem, Wayne Eric Burk, Michael Bekerman, Marc A Schaub
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GENERATION OF DUMMY FRAME IN IMAGE SENSOR INTERFACE CIRCUIT RESPONSIVE TO DETECTION OF TIMEOUT ERROR
Publication number: 20240305911Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.Type: ApplicationFiled: March 10, 2023Publication date: September 12, 2024Inventors: Wayne Eric Burk, Oren Kerem, Hoi Man S. Ng, Michael Bekerman -
Generation of dummy frame in image sensor interface circuit responsive to detection of timeout error
Patent number: 12081892Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.Type: GrantFiled: March 10, 2023Date of Patent: September 3, 2024Assignee: APPLE INC.Inventors: Wayne Eric Burk, Oren Kerem, Hoi Man S. Ng, Michael Bekerman -
Publication number: 20240232000Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.Type: ApplicationFiled: October 19, 2023Publication date: July 11, 2024Applicant: Apple Inc.Inventors: Marc A. Schaub, Roy G. Moss, Michael Bekerman
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Patent number: 12028437Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: GrantFiled: May 2, 2023Date of Patent: July 2, 2024Assignee: Apple Inc.Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Publication number: 20240134737Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.Type: ApplicationFiled: October 18, 2023Publication date: April 25, 2024Applicant: Apple Inc.Inventors: Marc A. Schaub, Roy G. Moss, Michael Bekerman
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Publication number: 20240107183Abstract: In some implementations, a method of synchronizing a content generation and delivery architecture to reduce the latency associated with image passthrough. The method includes: determining a temporal offset associated with the content generation and delivery architecture to reduce a photon-to-photon latency across the content generation and delivery architecture; obtaining a first reference rate associated with a portion of the content generation and delivery architecture; generating, via synchronization circuitry, a synchronization signal for the content generation and delivery architecture based at least in part on the first reference rate; and operating the content generation and delivery architecture according to the synchronization signal and the temporal offset.Type: ApplicationFiled: September 18, 2023Publication date: March 28, 2024Inventors: Joseph Cheung, Kaushik Raghunath, Michael Bekerman, Moinul H. Khan, Vivaan Bahl, Yung-Chin Chen, Yuqing Su
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Publication number: 20230388468Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Yung-Chin Chen, Michael Bekerman, Guy Côté, Aleksandr M. Movshovich, D. Amnon Silverstein, David R. Pope
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Patent number: 11829237Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.Type: GrantFiled: March 5, 2021Date of Patent: November 28, 2023Assignee: Apple Inc.Inventors: Marc A Schaub, Roy G. Moss, Michael Bekerman
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Publication number: 20230353339Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: ApplicationFiled: May 2, 2023Publication date: November 2, 2023Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Patent number: 11743440Abstract: In one embodiment, a system includes a first device rendering image data, a second device storing the image data, and a display panel that displays the image data stored in the memory. The first device renders multiple frames of the image data, compresses the multiple frames into a single superframe, and transports the single superframe. The second device receives the single superframe, decompresses the single superframe into the multiple frames of image data, and stores the image data on a memory of the second device.Type: GrantFiled: April 19, 2021Date of Patent: August 29, 2023Assignee: Apple Inc.Inventors: Yung-Chin Chen, Michael Bekerman, Guy Côté, Aleksandr M. Movshovich, D. Amnon Silverstein, David R. Pope
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Patent number: 11687115Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.Type: GrantFiled: September 22, 2021Date of Patent: June 27, 2023Assignee: Apple Inc.Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Patent number: 11683149Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: GrantFiled: September 10, 2021Date of Patent: June 20, 2023Assignee: Apple Inc.Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Publication number: 20230091434Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Kalpana Bansal, Michael Bekerman, Remi Clavel