Abstract: A data packet classifier to classify a plurality of N-bit input tuples, said classifier comprising a hash address, a memory and a comparison unit. The hash address generator generate a plurality of M-bit hash addresses from said plurality of N-bit input tuples, wherein M is significantly smaller than N. The memory has a plurality of memory entries and is addressable by said plurality of M-bit hash addresses, each such address corresponding to a plurality of memory entries, each of said plurality of memory entries capable of storing one of said plurality of N-bit tuples and an associated process flow information. The comparison unit determines if an incoming N-bit tuple can be matched with a stored N-bit tuple. The associated process flow information is output if a match is found and wherein a new entry is created in the memory for the incoming N-bit tuple if a match is not found.

Abstract: An apparatus for distributing processing loads in a service aware network is provided. The apparatus contains a controller and a plurality of packet processors coupled to the controller. The controller receives a first data packet and determines whether or not any of the packet processors have been previously selected to process the first data packet based on a classification of the first data packet. When none of the packet processors has been previously designated to process the first data packet, the controller selects a first selected processor of the packet processors to process the first data packet. The first selected processor is selected based on processing load values respectively corresponding to processing loads of the packet processors. In addition, a method performed by the apparatus and a software program for controlling the controller are also provided.

Abstract: A network interface that processes data packets transmitted on a network is provided. The network interface includes a first data path, a second data path, a header processor, a classifier unit, and a plurality of packet processors. The first data path unit inputs downstream data packets transmitted downstream on the network, and the second data path unit inputs upstream data packets transmitted upstream on the network. The header processor inputs data packet headers of the downstream and upstream data packets from the first and second data path units and classifies the downstream and upstream data packets by comparing the headers with predetermined rules. The classifier unit also inputs the data packet headers from the first and second data path units and evaluates the headers determine flows corresponding to the downstream and upstream data packets.

Abstract: A device for classifying input data based on the values of first and second data of the input data includes a content addressable memory having one or more rows. A first row includes first and second memories, first and second comparators, and a first hit line. The first memory stores second minimum and maximum values defining a second range. The first and second comparators determine whether or not the first and second data fall within the first and second ranges, respectively. The first hit line outputs a first logic value when the first data falls within the first range and the second data falls within the second range. Conversely, the first hit line outputs a second logic value when the first data falls outside the first range or the second data falls outside the second range.

Abstract: A system that efficiently and effectively monitors Internet protocol (IP) data being transferred in an asynchronous transfer mode (ATM) protocol and provides the information necessary according to a list of specified rules and a method and computer program product therefor are provided. The system allows for opening a process flow associated with the IP data such that the total amount of information about the process flow is reduced and the associated data is promptly recognized as belonging to a specific process flow. The system is capable of directing the data belonging to a certain process flow to an assigned network processor out of a plurality of such processors, while maintaining a balanced load between those processors.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further than notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: A method and related apparatus enables one station on a local area network (LAN) 24 to securely wake up another station on the LAN 24 although the stations may be physically remote from each other. A workstation 12, acting as a remote management console, generates a secure wake-up packet 42 intended for a desktop computer 14 on the LAN 24. The desktop computer 14 is operating in a sleep state. The data section of the secure wake-up packet has a particular sequence of data including a synchronization sequence 46, a MAC address sequence 48 and a password sequence 50. The desktop computer 14 has a network interface 64 for detecting and processing secure wake-up packets 70 when that network interface 64 is operating in a remote access control mode. The network interface 64 verifies that MAC address sequence 48 corresponds to the MAC address of the desktop computer 14 and that the password sequence 50 has a predetermined relationship with a password required to wake up the desktop computer 14.

Abstract: A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts occurring over an interface input/output (I/O) bus, a method and apparatus which transfers all status information directly to the host memory without host involvement. The host CPU is then notified of this new status information via an interrupt. When status information is transferred to the host memory, consistency is ensured and the number of spurious interrupts are reduced. A host software driver may then read the latest status information from the interface I/O bus at its convenience any not incur any performance penalties of I/O accesses.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field and a peak rate accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.

Abstract: A system for controlling the transmission of cells from a network node over multiple virtual circuit is disclosed. The disclosed system performs traffic shaping for all virtual circuits connected with the network node. The system includes a virtual circuit table with one or more entries. Each virtual circuit table entry corresponds to a virtual circuit established with the network node. Each virtual circuit table further includes one or more Cell Rate Accumulator fields and a Time Stamp field. The system includes a schedule table having one or more entries. Each schedule table entry further includes one or more Cell Rate Accumulator fields and corresponding predetermined value fields. A schedule table loading process determines a virtual circuit on which a packet is to be transmitted, and then calculates a time elapsed since a last previous write of a virtual circuit table entry corresponding with that virtual circuit.

Abstract: An Asynchronous Transfer Mode (ATM) network device having a receiver portion capable of receiving ATM cells on one of a number of virtual circuits (VCs) from an upstream ATM switch, a local memory used to store the ATM cells, a management system to manage the local memory using a number of queues, a system for assembling ATM cells into packets, a system for transmitting the packets to a host memory, and a transmitter portion having a system for indicating the transmitting of packets to the host memory to the upstream ATM switch.

Abstract: The invention improves the efficiency of buffer descriptor processing by performing descriptor prefetches, where multiple descriptors are read within the same descriptor bus transaction. The invention reads multiple buffer descriptors each time the bus is accessed. This allows for a smaller FIFO in a cut-through network adapter because it reduces the number of bus transactions needed to transfer data.

Abstract: An Asynchronous Transfer Mode (ATM) network adapter having a receiver portion, the receiver portion capable of receiving a first plurality of ATM cells and assembling the first plurality of ATM cells into a first plurality of packets, and a transmitter portion, the transmitter receiving a second plurality of packets and segmenting the second plurality of packets into a second plurality of ATM cells, the receiving portion having a local memory for segmentation, while the transmitter portion having no local memory.

Abstract: In an asynchronous transfer mode (ATM) endnode a method is provided by which ATM cells can experience a small delay from the ATM layer to the PHY layer to transmission on the ATM network.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field, a peak rate accumulator field, and a latency accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.

Abstract: A host system and an ATM network adapter using a chaser packet are presented. The adapter receives cells over a virtual connection on the network and generates, in response to the host system, a chaser packet which allows the host to detect that all data has been transferred form the adapter buffers to host memory. When all data has been transferred, the host may release the virtual connection without data loss. The host and adapter may also transmit data. In data transmission, the chaser packet is used to determine that all data has been transmitted out onto the network before the sending host releases the virtual connection. The chaser packet is also used for resynchronization of credits where the ATM network uses credit-based flow control. The adapter uses the chaser packet to drain the local queue so that the link between the adapter and a source system may be resynchronized.

Abstract: An asynchronous transfer mode (ATM) network device having a receiver portion, the receiver portion capable of receiving ATM cells on virtual circuits (VCs) from an upstream ATM switch, a local memory used to store the ATM cells, managing local memory using queues, assembling ATM cells into packets, transmitting the packets to a host memory, resynchronizing ATM credits, and a transmitter portion, the transmitter portion indicating transmitting of packets to host memory to the upstream ATM switch.