Abstract: Disclosed herein are examples of integrated circuit (IC) structures with engineered substrates that may mitigate problems that may be encountered when epitaxially growing III-N semiconductor materials, such as gallium nitride. Examples of engineered substrates for epitaxial growth of III-N semiconductor materials and III-N transistors include a thicker silicon substrate, a lattice-matched substrate, and a trap-rich silicon-on-insulator (SOI) substrate. In one example, an IC structure includes a lattice-matched and/or SOI substrate including a polycrystalline semiconductor material, an oxide layer over the polycrystalline semiconductor material, and a monocrystalline semiconductor material over the oxide layer. The IC structure may include a III-N semiconductor material over the monocrystalline silicon layer.

Abstract: Disclosed herein are examples of integrated circuit (IC) structures fabricated using semiconductor/dielectric interface engineering techniques for III-N transistors. Semiconductor/dielectric interface engineering techniques for III-N transistors may include, for example, a thermal treatment, a chemical treatment, a plasma treatment, and/or introduction of an interlayer (e.g., between the III-N semiconductor material and the gate insulator material and/or between the polarization material and an insulator material). The resulting semiconductor/dielectric interface may in turn result in higher performance and/or higher gate dielectric reliability.

Abstract: Disclosed herein are IC structures with III-N transistors and backside vias and associated packages, assemblies, and devices. In one example, an IC structure may include a substrate having a first side and a second side; a semiconductor material over the first side of the substrate, the semiconductor material including gallium and nitrogen; a first conductive backside via; and a second conductive backside via, in which: the first and the second conductive backside vias extend from the second side of the substrate to the first side of the substrate and into the semiconductor material, and a distance between the second side of the substrate and an end of the first conductive backside via in the semiconductor material is different from a distance between the second side of the substrate and an end of the second conductive backside via in the semiconductor material.

Abstract: Disclosed herein are IC structures with III-N transistors and features designed to enhance their performance, as well as packages, assemblies, and devices incorporating such IC structures. One such feature includes providing an oxide-nitride-oxide-nitride stack over the channel region of a III-N transistor. Another such feature is providing field plates extending from source and drain regions of a III-N transistor. Yet another feature is fabricating a III-N transistor with a curved gate. Still another feature is providing III-N transistors separated from one another by isolation structures with nitride liners.

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to low aluminum concentration aluminum gallium nitride interlayers for group III-nitride enhancement mode transistors. The low aluminum concentration aluminum gallium nitride interlayer includes a lower aluminum concentration than a polarization layer of the transistor, such that the polarization layer induces a two-dimensional electron gas in a semiconductor layer of the transistor. The low aluminum concentration aluminum gallium nitride interlayer may be implemented as an etch stop layer, as a gate liner, or both.

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.