Abstract: A bioengineering method which comprises introducing an inert nucleic acid cassette into a biological entity without introducing or modifying characteristics or traits in the biological entity. The method comprises receiving or providing a sample comprising the biological entity having a nucleic acid sequence; selecting an integration site in the nucleic acid sequence for inserting the inert nucleic acid cassette; designing the inert cassette with optimized primer sequences, optimized probe sequences, optimized stop codons and disrupted start codons, and inserting the inert nucleic acid cassette into the biological entity at the integration site; and validating that no characteristics have been added or modified in the biological entity.

Abstract: Provided herein are methods and compositions for providing identification and/or traceability of biological materials. In certain embodiments, methods are provided including steps of: determining a sequence of at least one unique identifier sequence in the genomic DNA of a biological entity; validating identification of the biological entity by verifying presence of the unique identifier sequence in the genomic DNA and comparing the sequence of the unique identifier sequence with a database to confirm uniqueness; providing an indication of acceptability to produce a biological material from the biological entity; and inputting the unique identifier sequence into a database entry of the database and associating the unique identifier sequence with identification and/or tracking information; thereby providing traceability by reading the unique identifier sequence and retrieving the corresponding database entry to obtain the identification and/or tracking information.

Abstract: The present disclosure is directed to a semiconductor package including a substrate having a lower surface with a plurality of slot structures. The plurality of slot structures are multi-layer structures that encourage the formation of solder joints. The semiconductor package is desirable for high reliability applications in which each solder joint termination should be checked by visual systems to ensure a proper electrical connection has been made.

Abstract: The present disclosure is directed to a semiconductor package including a substrate having a lower surface with a plurality of slot structures. The plurality of slot structures are multi-layer structures that encourage the formation of solder joints. The semiconductor package is desirable for high reliability applications in which each solder joint termination should be checked by visual systems to ensure a proper electrical connection has been made.

Abstract: A system may include an image database having a number of images, such that each of the images is linked to a respective organization of a number of organizations. The system may also include a financial database having financial information associated with the number of organizations. The system may also include a processor that receives image data representative of an object, determine an organization associated with the object based on a comparison of the image data with at least one image of the number of images in the image database and a correlation between the at least one image with the organization, and retrieve financial data regarding the organization from the financial database. The processor may then generate visualizations regarding the financial data and overlay the visualizations on the image data.

Abstract: A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant.

Abstract: A pixel circuit includes a pixel-capture device having a pixel node and operable to convert light intensity into a pixel signal at the pixel node, the pixel signal representing a captured pixel. A row node carries a row signal that is operable to both (a) enable passage of the pixel signal from the pixel node to a column node during a readout phase of the captured pixel, and (b) set the pixel node to a predetermined signal level during a reset phase of the captured pixel. The reset phase and the readout phase are configured to occur during different time intervals. A reset node is included for carrying a reset signal that is operable together with the row signal to (a) enable passage from the pixel node to the column node during the readout phase, and (b) set the pixel node to predetermined signal level during the reset phase.

Abstract: An action figure is provided with a serial number that provides an access code which allows owners to engage in enjoyable games or other activities via the Internet or other gaming systems. The interactive action figure system comprises a toy, statue, or other three-dimensional figurine with a serial number, and preferably a computer network accessible over the internet and a particular gaming framework managed by a network device. Owners of action figure toys may “log onto” the network using the action figure serial number as an access code to activate a particular computer character identity and participate in games such as hand-to-hand combat games, action-adventure series, or learning games. The action figure may be, for example, a warrior, sports figure, doll or teddy bear to appeal to a wide range of users. Once a particular character is activated, game play proceeds according to preset rules.

Abstract: An active pixel sensor array sampling system includes a plurality of video circuits and reset circuits. A video circuit generates a video voltage from each one of the pixels of a column of pixels. An associated reset circuit generates a reset voltage for each of the pixels of a column of pixels. The video circuits and the reset circuits are closed loop sample and hold circuits. The active pixel sensor array is integrated on an integrated circuit.

Abstract: A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant.

Abstract: A method and apparatus for optimizing the voltage supply of an image sensor pixel array to minimize pixel noise and maximize dynamic range is disclosed. The voltage supply is adjusted in response to the exposure level of the pixel array when it captures an image. The voltage supply is increased in higher exposure levels to expand the dynamic range of the pixel array. In lower exposure levels, when the full dynamic range of the pixel array is not utilized, the voltage supply is decreased to lower pixel noise level and reduce its effect on image quality.

Abstract: A method and apparatus for optimizing the voltage supply of an image sensor pixel array to minimize pixel noise and maximize dynamic range is disclosed. The voltage supply is adjusted in response to the exposure level of the pixel array when it captures an image. The voltage supply is increased in higher exposure levels to expand the dynamic range of the pixel array. In lower exposure levels, when the full dynamic range of the pixel array is not utilized, the voltage supply is decreased to lower pixel noise level and reduce its effect on image quality.

Abstract: An active pixel sensor array sampling system includes a plurality of video circuits and reset circuits. A video circuit generates a video voltage from each one of the pixels of a column of pixels. An associated reset circuit generates a reset voltage for each of the pixels of a column of pixels. The video circuits and the reset circuits are closed loop sample and hold circuits. The active pixel sensor array is integrated on an integrated circuit.

Abstract: A pixel circuit includes a pixel-capture device having a pixel node and operable to convert light intensity into a pixel signal at the pixel node, the pixel signal representing a captured pixel. A row node carries a row signal that is operable to both (a) enable passage of the pixel signal from the pixel node to a column node during a readout phase of the captured pixel, and (b) set the pixel node to a predetermined signal level during a reset phase of the captured pixel. The reset phase and the readout phase are configured to occur during different time intervals. A reset node is included for carrying a reset signal that is operable together with the row signal to (a) enable passage from the pixel node to the column node during the readout phase, and (b) set the pixel node to the predetermined signal level during the reset phase.

Abstract: An active pixel sensor array sampling system includes a plurality of video circuits and reset circuits. A video circuit generates a video voltage from each one of the pixels of a column of pixels. An associated reset circuit generates a reset voltage for each of the pixels of a column of pixels. The video circuits and the reset circuits are closed loop sample and hold circuits. The active pixel sensor array is integrated on an integrated circuit.

Abstract: A pixel circuit includes a silicon substrate having a photodiode that converts light intensity into a voltage signal and two metal layers disposed on the substrate having a pixel control circuit. The first metal layer includes a row trace and a reset trace and the second metal layer includes a column trace and a voltage supply trace. The row trace carries a signal that activates a switch for coupling the photodiode to the column trace during a readout phase and clears the voltage at the photodiode during a reset phase. The column trace interfaces with a signal capture circuit in a CMOS array of pixels for capturing a digital image that corresponds to each voltage level at each photodiode.