Patents by Inventor Michael Bourland

Michael Bourland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190107569
    Abstract: Aspects of the disclosure includes a transistor-under-test (TUT) to charge/discharge a capacitor; changing an oscillation state when a capacitor voltage crosses a threshold and turning OFF the TUT; discharging the capacitor using the TUT; commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; commencing discharging the capacitor after a precharger time delay; sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT; and generating a digital representation of a TUT current associated with a relaxation oscillator period of the relaxation oscillator waveform.
    Type: Application
    Filed: October 11, 2017
    Publication date: April 11, 2019
    Inventors: David Kidd, Ardavan Moassessi, Angelo Pinto, Albert Kumar, Yi Lou, Bipin Duggal, Amar Gulhane, Michael Bourland, Mustafa Badaroglu, Paul Penzes
  • Publication number: 20070126480
    Abstract: A fully differential peak detection circuit includes programmable sensitivity and an autozero function. The peak detector has a fully differential charge-coupled analog signal path. The entire analog signal path is autozeroed upon enable and/or in response to sensing a logic zero at the output, where the logic zero follows a logic one. The peak detector includes a differential gain stage for receiving an analog input signal. The differential gain stage includes offset error compensation. The offset error compensation is selected upon enable and/or in response to an output signal of the peak detection circuit and automatically zeros an offset error voltage in response to a predetermined logic state of the output signal. The output of the gain stage is provided to a comparator stage. A plurality of capacitors coupled to the comparator stage stores a predetermined voltage for setting a sensitivity of the peak detector.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Dale McQuirk, Michael Bourland