Abstract: Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

Abstract: A semiconductor wafer of monocrystalline silicon is produced, in the following order: growing a single crystal of silicon by the CZ method; dividing off a wafer consisting completely of an N region, in which there are no agglomerates of silicon interstitials or vacancies having a diameter of more than 20 nm, and has an oxygen concentration of not less than 5.3×1017 atoms/cm3 and not more than 5.9×1017 atoms/cm3 and a nitrogen concentration of not more than 1.0×1012 atoms/cm3; executing a three separate rapid thermal annealing (RTA) treatments of the wafer at temperatures within different temperature ranges over different time periods in a different atmospheres of argon with and without ammonia.

Abstract: The present disclosure relates to a calibrated constellation simulator, a system and a method for calibrating and/or testing a star sensor assembled on a spacecraft. The calibrated constellation simulator comprises an optical device configured to project a defined star formation (IRF) of a star catalog onto a star sensor assembled on a spacecraft. Further, the calibrated constellation simulator comprises an alignment unit with a position and/or location reference (ARF) of the calibrated constellation simulator configured to detect a position and/or location of the calibrated constellation simulator in space, wherein the defined star formation (IRF) and the position and/or location reference (ARF) are in a first fixed calibrated rotation (QOSPS) with respect to one another. The calibrated constellation simulator improves the calibration of the star sensor as an independent calibration standard. The constellation simulator becomes a calibration standard.

Abstract: Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.

Abstract: A method produces a single-crystal silicon semiconductor wafer. A single-crystal silicon substrate wafer is double side polished. A front side of the substrate wafer is chemical mechanical polished (CMP). An epitaxial layer of single-crystal silicon is deposited on the front side of the substrate wafer. A first rapid thermal anneal (RTA) treatment is performed on the coated substrate wafer at 1275-1295° C. for 15-30 seconds in argon and oxygen, having oxygen of 0.5-2.0 vol %. The coated substrate wafer is then cooled at or below 800° C., with 100 vol % argon. A second RTA treatment is performed on the coated substrate wafer at a 1280-1300° C. for 20-35 seconds in argon. An oxide layer is removed from a front side of the coated substrate wafer. The front side of the coated substrate wafer is polished by CMP.

Abstract: A method produces a single-crystal silicon semiconductor wafer. A single-crystal silicon substrate wafer is double side polished. A front side of the substrate wafer is chemical mechanical polished (CMP). An epitaxial layer of single-crystal silicon is deposited on the front side of the substrate wafer. A first rapid thermal anneal (RTA) treatment is performed on the coated substrate wafer at 1275-1295° C. for 15-30 seconds in argon and oxygen, having oxygen of 0.5-2.0 vol %. The coated substrate wafer is then cooled at or below 800° C., with 100 vol % argon. A second RTA treatment is performed on the coated substrate wafer at a 1280-1300° C. for 20-35 seconds in argon. An oxide layer is removed from a front side of the coated substrate wafer. The front side of the coated substrate wafer is polished by CMP.

Abstract: Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

Abstract: Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.

Abstract: A semiconductor wafer of single-crystal silicon includes: a polished front side and a back side; a denuded zone, which extends from the polished front side toward the back side to a depth of not less than 45 ?m; and a region adjacent to the denuded zone, the region having bulk micro defect (BMD) seeds, which are capable of being developed into BMDs. A density of the BMDs at a distance of 120 ?m from the front side is not less than 3×109 cm?3.

Abstract: A circuit structure having at least one capacitor and a method for the manufacture thereof. The capacitor is constructed of a doped, single-crystal silicon substrate (1) that is provided with a plurality of hole openings (3) by electrochemical etching in a fluoride-containing, acidic electrolyte wherein the substrate is connected as an anode. The capacitor is further constructed of a dielectric layer (4) and of a conductive layer (5) as a cooperating electrode.