Abstract: A processor including a logic unit configured to execute multiple instructions being one of a speculative instruction or an architectural instruction is provided. The processor also includes a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction. The processor includes a cache manager configured to select a number of speculative lines allocated in the split cache. The cache manager prevents an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manages the number of speculative lines to be allocated in the split cache based on the number of speculative lines relative to a number of architectural lines.

Abstract: Systems and methods are provided to allow configuration of network devices via a Bluetooth® (or other short range wireless) configuration network using a mesh network implementation. This configuration mesh network may represent a mesh network independent of any active wired or production network within an enterprise computer system. For security of a network infrastructure for the enterprise computer system, wired ports on network infrastructure devices may be disabled prior to configuration via the configuration mesh network. New devices may be physically but not communicatively connected to the production network (e.g., cables may be connected to disabled ports) and then configuration may be performed via the configuration mesh network to allow the new devices to become active (e.g., join with production devices) within the network infrastructure. Run-time configurations for production devices may also be maintained using a separate configuration mesh network.

Abstract: Systems and methods are provided to allow configuration of network devices via a Bluetooth® (or other short range wireless) configuration network using a mesh network implementation. This configuration mesh network may represent a mesh network independent of any active wired or production network within an enterprise computer system. For security of a network infrastructure for the enterprise computer system, wired ports on network infrastructure devices may be disabled prior to configuration via the configuration mesh network. New devices may be physically but not communicatively connected to the production network (e.g., cables may be connected to disabled ports) and then configuration may be performed via the configuration mesh network to allow the new devices to become active (e.g., join with production devices) within the network infrastructure. Run-time configurations for production devices may also be maintained using a separate configuration mesh network.

Abstract: A processor including a logic unit configured to execute multiple instructions being one of a speculative instruction or an architectural instruction is provided. The processor also includes a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction. The processor includes a cache manager configured to select a number of speculative lines allocated in the split cache. The cache manager prevents an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manages the number of speculative lines to be allocated in the split cache based on the number of speculative lines relative to a number of architectural lines.

Abstract: A device including a logic unit configured to execute multiple instructions, and a schedule buffer that lists the instructions to be executed by the logic unit is provided. The device includes a fetch engine to retrieve data from an external memory, a cache including lines to hold the data associated with one of the instructions, including a spec-bit. The device includes a management unit to set the spec-bit to a speculative state when the data is retrieved for an instruction that has not been committed for execution by the logic unit, and to reset the spec-bit from a speculative state to a trusted state for a valid instruction. The management unit prevents the data from remaining in the cache when the spec-bit is in a speculative state. A computer system including the above device and a method of using the device are also provided.

Abstract: Techniques for providing a system wide manageability interface are provided. In one aspect, manageability data may be received from a plurality of manageability subsystems. Each manageability subsystem may be contained in a domain. The received manageability data may be coalesced into a system wide view. The system wide view may span all domains.

Abstract: Techniques for providing a system wide manageability interface are provided. In one aspect, manageability data may be received from a plurality of manageability subsystems. Each manageability subsystem may be contained in a domain. The received manageability data may be coalesced into a system wide view. The system wide view may span all domains.

Abstract: A closed-loop controller of an apparatus in an example operates a set of switches to dynamically configure power rails to an industry-standard socket.

Abstract: An apparatus is provided to display errors. The apparatus includes an error display module, a memory, and a processor. The error display module to provide a collection of error data. The collection of error data for at least one error from an electronic component. The memory to store a set of instructions. The processor coupled to the memory. The set of instructions instructing the processor to store the collection of error data and display the collection of error data without using power from the electronic component.

Abstract: A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.

Abstract: A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

Abstract: A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.

Abstract: A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

Abstract: Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module.

Abstract: A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs) through employment of a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol).

Abstract: Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.

Abstract: A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

Abstract: A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch.

Abstract: A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.

Abstract: Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.