Patents by Inventor Michael Brian White

Michael Brian White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple uses for BIST test latches
    Patent number: 8006153
    Abstract: A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven Ross Ferguson, Garrett Stephen Koch, Osamu Takahashi, Michael Brian White
  • Multiple uses for BIST test latches
    Patent number: 7574642
    Abstract: A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: August 11, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven Ross Ferguson, Garrett Stephen Koch, Osamu Takahashi, Michael Brian White
  • MULTIPLE USES FOR BIST TEST LATCHES
    Publication number: 20080313512
    Abstract: A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
    Type: Application
    Filed: August 25, 2008
    Publication date: December 18, 2008
    Inventors: Steven Ross Ferguson, Garrett Stephen Koch, Osamu Takahashi, Michael Brian White
  • Memory array manufacturing defect detection system and method
    Patent number: 7318182
    Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: January 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Louis Bernard Bushard, Sang Hoo Dhong, Brian King Flachs, Osamu Takahashi, Michael Brian White