Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Abstract: An integrated semiconductor device includes a silicon body that includes <111> single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device.

Abstract: A semiconductor structure includes a substrate, a first graded transition body over the substrate, a second transition body and a III-Nitride semiconductor layer over the second transition body. The first graded transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The second transition body has a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body. The second transition body includes at least two transition modules each having at least three interlayers. The first graded transition body and the second transition body reducing strain for the semiconductor structure.

Abstract: A semiconductor structure includes a substrate, a transition body over the substrate, a group III-V intermediate body having a bottom surface over the transition body and a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a first impurity concentration at the bottom surface, a second impurity concentration at the top surface, and a variable impurity concentration that rises and falls between the bottom surface and the top surface. The first impurity concentration is greater than the second impurity concentration.

Abstract: In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors.

Abstract: A semiconductor structure includes a substrate, a transition body over the substrate, a group III-V intermediate body having a bottom surface over the transition body and a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a first impurity concentration at the bottom surface, a second impurity concentration at the top surface, and a variable impurity concentration that rises and falls between the bottom surface and the top surface. The first impurity concentration is greater than the second impurity concentration.

Abstract: A semiconductor structure includes a substrate, a first graded transition body over the substrate a second transition body and a III-Nitride semiconductor layer over the second transition body. The first graded transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The second transition body has a smaller lattice parameter at a lower surface overlying the second surface of the first graded transition body and a larger lattice parameter at an upper surface of the second transition body. The second transition hod includes at least two transition modules each having at least three interlayers. The first graded transition body and the second transition body reducing strain for the semiconductor structure.

Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Abstract: According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Abstract: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.

Abstract: There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Abstract: A power converter driver that is supplied with two different voltages.

Abstract: According to an exemplary implementation, a transistor includes drain finger electrodes interdigitated with source finger electrodes. The transistor also includes a current conduction path in a semiconductor substrate between the drain finger electrodes and the source finger electrodes. At least one of the drain finger electrodes has a drain finger electrode end and a drain finger electrode main body, where the drain finger electrode main body is non-coplaner with at least a portion of the drain finger electrode end. The transistor may also include a dielectric material situated between at least a portion of the drain finger electrode end and the semiconductor substrate. The dielectric material can be an increasing thickness dielectric material. The dielectric material can thus elevate the drain finger electrode end over the semiconductor substrate. Further, the drain finger electrode end can have an increased radius of curvature.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.

Abstract: In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. The III-nitride semiconductor device also includes a gate arrangement situated in the gate well and including a gate electrode and a field plate. The field plate includes at least two steps, the at least two steps being defined in the dielectric body.