Abstract: Techniques for adjusting the voltage across an active filter element include a controlled circuit element and a control circuit element adapted to control the voltage across the controlled circuit element to increase transient load response and to reduce power dissipation.

Abstract: Techniques for adjusting the voltage across an active filter element include a controlled circuit element and a control circuit element adapted to control the voltage across the controlled circuit element to increase transient load response and to reduce power dissipation.

Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.

Abstract: A method of fabricating a HI-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.

Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.

Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.

Abstract: Techniques for reducing noise generated by a circuit include a common mode filter and a differential mode filter. The common mode filter includes an input for sensing a common mode signal between a power source and the circuit, an output, and active circuitry for producing an offset signal on the output. The differential mode filter includes an input, an output, and active circuitry for sensing a differential mode signal and producing variations in resistance between the input and output to offset the differential signal.

Abstract: Techniques for reducing noise generated by a circuit include a common mode filter and a differential mode filter. The common mode filter includes an input for sensing a common mode signal between a power source and the circuit, an output, and active circuitry for producing an offset signal on the output. The differential mode filter includes an input, an output, and active circuitry for sensing a differential mode signal and producing variations in resistance between the input and output to offset the differential signal.

Abstract: In accordance with one embodiment of the invention, a semiconductor device includes conductive pad areas, and each conductive pad area is electrically connected to a plurality of metal traces which are in turn each connected to diffusions. A conductive contact element such as a solder bump or via can be attached to each conductive pad area such that the contact elements are arranged in a repeating pattern having a first pitch. The semiconductor device can also include translation traces, and each translation trace can be electrically connected to two or more of the conductive contact elements. Each translation trace can have a interconnect element attached thereto. The interconnect elements can be arranged in a repeating pattern having a second pitch substantially greater than the first pitch.