Patents by Inventor Michael Bruennert
Michael Bruennert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7928525Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: GrantFiled: April 25, 2008Date of Patent: April 19, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20110080796Abstract: An integrated circuit is disclosed. One embodiment provides a sense amplifier; a first bit line; a second bit line. A first switch is configured to connect/disconnect the first bit line to/from the sense amplifier. A second switch is configured to connect/disconnect the second bit line to/from the sense amplifier independently from the first switch.Type: ApplicationFiled: November 20, 2007Publication date: April 7, 2011Applicant: QIMONDA AGInventors: Michael Bruennert, Harald Roth
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Patent number: 7920433Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.Type: GrantFiled: January 9, 2008Date of Patent: April 5, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20110034045Abstract: Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device.Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Patent number: 7848153Abstract: Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.Type: GrantFiled: August 19, 2008Date of Patent: December 7, 2010Assignee: Qimonda AGInventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gaertner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
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Patent number: 7796446Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.Type: GrantFiled: September 19, 2008Date of Patent: September 14, 2010Assignee: Qimonda AGInventors: Hermann Ruckerbauer, Michael Bruennert, Ullrich Menczigar, Christian Mueller, Sitt Tontisirin, Georg Braun, Dominique Savignac
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Patent number: 7771206Abstract: Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.Type: GrantFiled: September 11, 2008Date of Patent: August 10, 2010Assignee: Qimonda AGInventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gärtner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
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Patent number: 7764755Abstract: A method of synchronization of a digital circuit includes selecting a first site and a second site from a plurality of different sites of the digital circuit where a signal to be synchronized occurs; passing a first signal, which is the signal to be synchronized of the first site, via a first line that starts at the first site, ends at the second site, and contacts each of the sites just once, to the second site; passing a second signal, which is the signal to be synchronized of the second site, via a second line that starts at the second site, ends at the first site, and contacts each of the sites just once, to the first site; determining, for each site, a first phase shift between the signal to be synchronized of this site and the first signal, and a second phase shift between the signal to be synchronized of this site and the second signal; and determining, from the first and second phase shifts of each site, a delay for each site, with which the signal to be synchronized of the respective site is delayedType: GrantFiled: December 22, 2006Date of Patent: July 27, 2010Assignee: Qimonda AGInventors: Michael Brünnert, Paul Georg Lindt
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Publication number: 20100082871Abstract: Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.Type: ApplicationFiled: December 4, 2008Publication date: April 1, 2010Inventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gartner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
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Publication number: 20100074038Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.Type: ApplicationFiled: September 19, 2008Publication date: March 25, 2010Inventors: Hermann Ruckerbauer, Michael Bruennert, Ullrich Menczigar, Christian Mueller, Sitt Tontisirin, Georg Braun, Dominique Savignac
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Publication number: 20100062621Abstract: Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Inventors: MICHAEL BRUENNERT, Peter Gregorius, Georg Braun, Andreas Gartner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
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Publication number: 20100044877Abstract: An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.Type: ApplicationFiled: August 21, 2008Publication date: February 25, 2010Inventors: Michael Bruennert, Ullrich Menczigar, Christian Mueller, Sitt Tontosirin, Hermann Ruckerbauer
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Publication number: 20100046266Abstract: Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gaertner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
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Publication number: 20100032820Abstract: Memory modules, computing systems, and methods of manufacturing memory modules are disclosed. In one embodiment, a memory module includes a substrate having a first side and a second side opposed to the first side. A plurality of pins is disposed on the first side of the substrate. A first plurality of memory chips are arranged in a first chip layer, the first chip layer overlying the second side of the substrate. Electrical contacts of the first plurality of memory chips are electrically coupled to the pins. A second plurality of memory chips is arranged in a second chip layer, the second chip layer overlying the first chip layer. Electrical contacts of the second plurality of memory chips are electrically coupled to the pins.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Inventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gaertner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
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Publication number: 20100030934Abstract: A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Inventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gaertner, Hermann Ruckerbauer, George Alexander, Johannes Stecker
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Publication number: 20090287957Abstract: A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell.Type: ApplicationFiled: May 16, 2008Publication date: November 19, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler
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Publication number: 20090267678Abstract: An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090267084Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090190432Abstract: A DRAM chip with a data I/O-interface of an access width equal to a page size.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Inventors: Christoph BILGER, Peter GREGORIUS, Michael BRUENNERT, Maurizio SKERJI, Wolfgang WALTHES, Johannes STECKER, Hermann RUCKERBAUER, Dirk SCHEIDELER, Roland BARTH
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Publication number: 20090175115Abstract: Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler