Abstract: There is provided a data processing apparatus in which prediction circuitry stores a plurality of mappings from instructions to payloads. Query circuitry responds to a reference to one of the instructions provided as at least part of an input by outputting one of the payloads that maps to the one of the instructions. The payloads include one of a plurality of predictions and a prediction type that indicates which of a plurality of data speculation techniques the one of a plurality of predictions relates. The prediction circuitry stores, for each of the instructions, the prediction type as one of a plurality of different prediction types.

Abstract: Embodiments of the present disclosure include techniques for managing dirty data. An agent receives a request for data. If the data is dirty data, the agent may use a replacement policy to determine if the data should be passed clean or dirty to the requestor. The replacement policy may correspond to how long the dirty data being stored in a cache line is to be maintained. In one embodiment, the replacement policy is a circuit, such as an SRAM and a logic circuit, for example.

Abstract: Embodiments of the present disclosure include techniques for managing dirty data. An agent receives a request for data. If the data is dirty data, the agent may use a replacement policy to determine if the data should be passed clean or dirty to the requestor. The replacement policy may correspond to how long the dirty data being stored in a cache line is to be maintained. In one embodiment, the replacement policy is a circuit, such as an SRAM and a logic circuit, for example.

Abstract: Embodiments of the present disclosure include techniques for managing dirty data. An agent receives a request for data. If the data is dirty data, the agent may use a replacement policy to determine if the data should be passed clean or dirty to the requestor. The replacement policy may correspond to how long the dirty data being stored in a cache line is to be maintained. In one embodiment, the replacement policy is a circuit, such as an SRAM and a logic circuit, for example.

Abstract: A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

Abstract: A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

Abstract: Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.