Abstract: Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Abstract: Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Abstract: A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Abstract: A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.

Abstract: A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.

Abstract: A computer system includes a memory controller interfacing the processor to a memory system. The memory controller supports a memory system with a plurality of memory devices, with multiple memory banks in each memory device. The memory controller supports simultaneous memory accesses to different memory banks. Memory bank conflicts are avoided by examining each transaction before it is loaded in the memory transaction queue. On a first clock cycle, the new pending memory request is transferred from a pending request queue to a memory mapper. On the subsequent clock cycle, the memory mapper formats the pending memory request into separate signals identifying the DEVICE, BANK, ROW and COLUMN to be accessed by the pending transaction. In the next clock cycle, the DEVICE and BANK signals are compared with every entry in the memory transaction queue to determine if a bank conflict exists. If so, the new memory request is rejected and recycled to the pending request queue.

Abstract: A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield.