Abstract: A hardware/software co-simulation permits access to a server state from any process in the hardware/software co-simulation. In one embodiment, a co-simulation interface receives a request from a client system for configuration data for the server state in of the hardware/software co-simulation. The configuration data defines memory locations in the co-simulation from which the server state can be assembled. The interface inserts the request in the co-simulation. The co-simulation responds with the configuration information. Based on the configuration information, memory operations can be performed on the server state.

Abstract: An IP package is formed with at least one of one or more components of an IP block and one or more pointers to locations where the components can be retrieved, and machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block in an integrated circuit. In one embodiment, the connectivity descriptions include physical pin, implemented bus signals, handling of unimplemented bus signals, and mapping descriptions. In various embodiments, the IP package may further include one or more selected ones of customizable attribute, UI choice elements, embedded and/or diagnostic software, test vectors, supplemental generators and verification environment configuration requirement descriptions. The self-describing packaging advantageously enables an EDA tool suite to offer and facilitate selection of the IP block for a SOC design.

Abstract: Enhanced Platform Based SOC Design Including Extended Peripheral Selection and Automated IP Customization Facilitation An EDA tool suite is provided to facilitate SOC design in a platform based manner, by first facilitating the selection of a compute engine, then supporting peripheral devices layered upon the compute engine in at least a single peripheral layer. In various embodiments, the EDA tool suite includes pre-processing functions to identify connectivity of an IP component, and automatic creation of a user interface to facilitate provision of customization inputs. The EDA tool suite further includes bus bridges bridging a plurality of bus architecture pairs, and component selection facilities that automatically provides an expanded list of components for selection, including components connectable to a selected compute engine by way of a pre-provided bus bridge, responsive to the selection of the compute engine.

Abstract: An IP package is formed with at least one of one or more components of an IP block and one or more pointers to locations where the components can be retrieved, and machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block in an integrated circuit. In one embodiment, the connectivity descriptions include physical pin, implemented bus signals, handling of unimplemented bus signals, and mapping descriptions. In various embodiments, the IP package may further include one or more selected ones of customizable attribute, UI choice elements, embedded and/or diagnostic software, test vectors, supplemental generators and verification environment configuration requirement descriptions. The self-describing packaging advantageously enables an EDA tool suite to offer and facilitate selection of the IP block for a SOC design.

Abstract: An EDA tool suite is equipped with the ability to responsively invoke a chain of one or more generators corresponding to one or more phases of a design/verification process to process design information of IP blocks forming a SOC design to transform the design information, as a result of each invocation, from one state to another state. In one embodiment, the phases may be one or more of a design generation phase, a simulation hardware logic generation phase, an embedded/diagnostic software generation phase, and a verification environment configuration script generation phase.

Abstract: A method and apparatus for state management in a co-verification system is described. The invention allows acceleration of co-simulation without loss of information that can occur from independent simulation of software and hardware components of a design. For example, counters included in a hardware component that are influenced by software components are simulated and updated by the software simulator when simulation of hardware and software is not synchronized. When the counter or other hardware component that is maintained by software simulation causes a hardware event (e.g., an interrupt) to occur, co-simulation is resynchronized and the hardware component is updated. Improved acceleration of co-simulation is thereby provided.

Abstract: A method and apparatus for state management in a co-verification system is described. The invention allows acceleration of co-simulation without loss of information that can occur from independent simulation of software and hardware components of a design. For example, counters included in a hardware component that are influenced by software components are simulated and updated by the software simulator when simulation of hardware and software is not synchronized. When the counter or other hardware component that is maintained by software simulation causes a hardware event (e.g., an interrupt) to occur, co-simulation is resynchronized and the hardware component is updated. Improved acceleration of co-simulation is thereby provided.