Abstract: Higher voltage device isolation structures (40, 60, 70, 80, 90, 90?) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24?). One or more dielectric lined deep isolation trenches (27, 27?, 27?, 27??) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22?) is found to occur preferentially where the buried layer (24, 24?) intersects the dielectric sidewalls (273, 274; 273?, 274?; 273?, 274?) of the trench (27, 27?, 27?, 27??). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42?, 62, 72, 82) of the same conductivity type as the buried layer (24, 24?), underlying the buried layer (24, 24?) at the trench sidewalls (273, 274; 273?, 274?; 273?, 274?).

Abstract: A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.

Abstract: A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.