Abstract: A fuser assembly for an electrophotographic imaging device includes a heater including a substrate, a resistive trace disposed and running along a length of the substrate for generating heat for fusing toner to a sheet of media when a current is passed therethrough, and at least three conductors for passing current through the resistive trace. The at least three conductors include a first conductor connected to a first end portion of the resistive trace, a second conductor connected to a second end portion of the resistive trace, and a third conductor connected to the resistive trace at a location between the first end portion and the second end portion thereof. A temperature sensor senses a temperature of an edge segment of the substrate. Based upon the temperature sensed, circuitry selects between the first conductor and the third conductor for passing current through the resistive trace.

Abstract: Disclosed is a system for transitioning between views in a network page. An application that is executed in at least one computing device encodes a network page for rendering in a client, the network page including a region, and the region being configured for the rendering of at least two views. The network page is encoded to depict a transition between the two views. A first one of the views depicts at least one mechanism to add a depicted item in the network page to a list, and a second one of the views depicts at least a portion of the list. Once encoded, the network page is sent to the client.

Abstract: Disclosed is a system for transitioning between views in a network page. An application that is executed in at least one computing device encodes a network page for rendering in a client, the network page including a region, and the region being configured for the rendering of at least two views. The network page is encoded to depict a transition between the two views. A first one of the views depicts at least one mechanism to add a depicted item in the network page to a list, and a second one of the views depicts at least a portion of the list. Once encoded, the network page is sent to the client.

Abstract: A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Abstract: One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

Abstract: A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Abstract: A circuit comprising is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.

Abstract: The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.