Abstract: Correction for harmonic disturbances on rotating storage media in a phase-locked loop. The effects of harmonic disturbances in a phase-locked loop are reduced by employing harmonic correction. Harmonic correction may be present in the loop at all times, or may be switched in once the loop has achieved phase lock. Disturbance within the loop bandwidth is corrected using additional integrating pole or a bump (resonant) filter. Disturbance outside the loop bandwidth is corrected using low pass or a notch (anti-resonant) filter. Alternately, a canceling signal may be generated and added as a feedforward signal. A repetitive control scheme uses a filtered version of the residual errors on previous media rotations as a feedforward signal to cancel harmonic effects.

Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. Address lines and power lines of each array are connected to the array so that only the data storage diode cells of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the array. A controller enables the row and column address lines to selectively address a diode cell in a selected array.

Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. The address lines and power lines of the plurality of arrays are connected to the arrays so that only the data storage diode cells in the array of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the data storage unit.

Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. Address lines and power lines of each array are connected to the array so that only the data storage diode cells of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the array. A controller enables the row and column address lines to selectively address a diode cell in a selected array.

Abstract: Correction for harmonic disturbances on rotating storage media in a phase-locked loop. The effects of harmonic disturbances in a phase-locked loop are reduced by employing harmonic correction. Harmonic correction may be present in the loop at all times, or may be switched in once the loop has achieved phase lock. Disturbance within the loop bandwidth is corrected using additional integrating pole or a bump (resonant) filter. Disturbance outside the loop bandwidth is corrected using low pass or a notch (anti-resonant) filter. Alternately, a canceling signal may be generated and added as a feedforward signal. A repetitive control scheme uses a filtered version of the residual errors on previous media rotations as a feedforward signal to cancel harmonic effects.

Abstract: A circuit for recovering the timing reference signal includes a superheterodyne phase locked loop. The recovery circuit avoids the need for a phase linear filter with a large percentage bandwidth and allows placement of the filter at a point in the recovery circuit where the center frequency to be passed is substantially fixed. The recovery circuit thus constructed further allows the bandwidth of the filter to be narrower and tailored to match the modulation characteristics of the timing recovery signal. This further results in a better signal-to-noise ratio into a limiter and phase detector, improving the performance of the phase locked loop.

Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. The address lines and power lines of the plurality of arrays are connected to the arrays so that only the data storage diode cells in the array of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the data storage unit.

Abstract: Correction for harmonic disturbances on rotating storage media in a phase-locked loop. The effects of harmonic disturbances in a phase-locked loop are reduced by employing harmonic correction. Harmonic correction may be present in the loop at all times, or may be switched in once the loop has achieved phase lock. Disturbance within the loop bandwidth is corrected using additional integrating pole or a bump (resonant) filter. Disturbance outside the loop bandwidth is corrected using low pass or a notch (anti-resonant) filter. Alternately, a canceling signal may be generated and added as a feedforward signal. A repetitive control scheme uses a filtered version of the residual errors on previous media rotations as a feedforward signal to cancel harmonic effects.

Abstract: A method for synchronizing newly recorded data with previously recorded data. The method is implemented within a disk-based data storage system. A first difference between a wobble reference signal and previously recorded data is measured. Test data is written on a test track to measure a second difference between the wobble reference signal and the test data. The test data is written synchronously with a write clock. An offset value is determined by comparing the first difference and the second difference. New data is then written using the write clock and the offset value such that the new data is synchronized with the old data. To determine the offset value, the test data can be written to the test track with a write clock calibration delay set to zero, the test data can then be read from the test track and the first difference can be subtracted from the second difference to determine the offset value for the write clock calibration delay.

Abstract: An apparatus and method for adjusting the phase of an output digital signal while maintaining the symmetry of the input signal. The apparatus includes an input waveform signal and a comparator having a positive feedback path to an input and an output. An adjustable resistor is connected along the positive feedback path to the output of the comparator and to the positive input of the comparator. The apparatus produces an output waveform signal shifted in phase from the input waveform signal with the same duty cycle as the input waveform signal.

Abstract: A data decoder for decoding digital data in a high frequency signal in an optical storage device. A carrier signal derived from the high frequency passed through a zonal bandpass filter and a limiter is multiplied by the high frequency signal passed through a high pass filter. The resulting product is filtered and passed through a comparator forming a digital data stream.

Abstract: A phase detector is disclosed that detects the phase of two inputs with precision. A method and apparatus of phase detecting that subtracts out common errors due to temperature variations and supply voltage fluctuations. The phase detector and method preferably utilize digital circuitry such as exclusive OR gates and differential amplifiers to perform the accurate phase detection. The inputs and outputs may be attenuated or filtered to produce the desired results.

Abstract: Method and apparatus for recovering a timing reference signal in an optical storage subsystem. The timing reference signal is recovered by passing it through a zonal bandpass filter coupled to a hard limiter, which feeds a phase locked loop that produces the reference signal.

Abstract: An input carrier signal is applied to two paths. The two paths are such that the phase difference between the output of the two paths is substantially 90.degree.. At least one of the two paths responds to a modulating signal to select the polarity of the phase difference between the outputs of the two paths. The two paths are such that the phase angle between the output and input of the modulator is substantially independent of the amplitude of the modulating signal. In specific embodiments, one of the two paths includes a mixer or a quadrature hybrid with reflective diodes where the mixer or the diodes are operated in saturation. The outputs of the two paths are combined to provide a modulated carrier signal.

Abstract: Method and apparatus for amplification of an electrical signal whose frequency may range from zero to 300 MHz, and whose voltage level may range from 0.5 volt to 0.5 volt, with intermittent resetting of the zero voltage level provided for. One or two incoming signals are divided into low frequency and high frequency components, and amplification of each of these components is optimized by passage of the component through a separate amplification circuit. Input signals to the high and low frequency amplification circuits are intermittently chopped to allow resetting of the zero voltage levels of the amplifier.

Abstract: Two input signals of uncertain phase relationship are applied to trigger circuits which develop sharply defined logic level transitions in response to the input signals crossing predetermined amplitude threshold levels. These logic level transitions are then used to clock a register whose outputs are gated and filtered to provide a DC output signal whose level indicates the phase difference between the two input signals.

Abstract: A method and apparatus utilizing a quartz crystal resonator with an orientation substantially equal to (yxwl) 21.93.degree./33.93.degree. vibrating simultaneously in two thickness modes to provide a stable frequency signal source. By combining a quartz crystal resonator of the above type with either digital or analog compensation, the frequency-temperature deviation of one of the crystal mode frequencies is used as an internal thermometer and the second crystal mode frequency as a reference frequency signal. The frequency signal for the thermometer function is utilized by the compensation network to stabilize the frequency of the reference signal. Additionally, the analog or digital compensation is accomplished by means of either a curve-fitting routine or an interpolation look-up table routine.

Abstract: A method and apparatus utilizing a quartz crystal resonator with an orientation substantially equal to (yxwl) 21.93.degree./33.93.degree. vibrating simultaneously in two thickness modes to accurately measure temperature and unknown frequencies or to provide a stable frequency signal source. By combining a quartz crystal resonator of the above type with either digital or analog compensation, the frequency-temperature deviation of one of the crystal mode frequencies is used as an internal thermometer and the second crystal mode frequency as a reference frequency signal. The frequency signal for the thermometer function is utilized by the compensation network to correct the measurements made with, or to stabilize, the frequency of the reference frequency signal. Additionally, the analog or digital compensation is accomplished by means of either a curve-fitting routine or an interpolation look-up table routine.