Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: A method of forming a memory device that in one embodiment may include forming a magnetic tunnel junction on a first electrode using an electrically conductive mask and subtractive etch method. Following formation of the magnetic tunnel junction, at least one dielectric layer is deposited to encapsulate the magnetic tunnel junction. Ion beam etching/Ion beam milling may then remove the portion of the at least one dielectric layer that is present on the electrically conductive mask, wherein a remaining portion of the at least one dielectric layer is present over the first electrode. A second electrode may then be formed in contact with the electrically conductive mask.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.