Patents by Inventor Michael C. Harmes

Michael C. Harmes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-dimensional stacked substrate arrangements
    Patent number: 8421225
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS
    Publication number: 20120280387
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 8, 2012
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Three-dimensional stacked substrate arrangements
    Patent number: 8203208
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 19, 2012
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS
    Publication number: 20110260319
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Application
    Filed: May 9, 2011
    Publication date: October 27, 2011
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Three-dimensional stacked substrate arrangements
    Patent number: 7973407
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Three-dimensional stacked substrate arrangements
    Publication number: 20090174070
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 9, 2009
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobnnsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Method and structure for interfacing electronic devices
    Patent number: 7348217
    Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, R. Scott List, Sarah E. Kim, Michael C. Harmes
  • Method and structure for interfacing electronic devices
    Patent number: 6870270
    Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
    Type: Grant
    Filed: December 28, 2002
    Date of Patent: March 22, 2005
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, R. Scott List, Sarah E. Kim, Michael C. Harmes
  • Method and structure for interfacing electronic devices
    Publication number: 20040232537
    Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.
    Type: Application
    Filed: December 28, 2002
    Publication date: November 25, 2004
    Inventors: Mauro J. Kobrinsky, R. Scott List, Sarah E. Kim, Michael C. Harmes