Patents by Inventor Michael C. Harris

Michael C. Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4873629
    Abstract: A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions within the central processor (156). Instructions are transferred from the main memory (99) into a register (180) where the address fields of the instructions are decoded to produce a cracked instruction and these instructions are stored in a logical instruction cache (210). As the cracked instructions are selected they are transferred to an output buffer and decoder (214) where the remaining fields of the instructions are decoded to produce instruction execution commands.
    Type: Grant
    Filed: December 15, 1987
    Date of Patent: October 10, 1989
    Assignee: Convex Computer Corporation
    Inventors: Michael C. Harris, David M. Chastain, Gary B. Gostin
  • Patent number: 4620275
    Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.
    Type: Grant
    Filed: June 20, 1984
    Date of Patent: October 28, 1986
    Inventors: Steven J. Wallach, Thomas M. Jones, Frank J. Marshall, David A. Nobles, Kent A. Fuka, Steven M. Rowan, William H. Wallace, Harold W. Dozier, David M. Chastain, John W. Clark, Robert B. Kolstad, James E. Mankovich, Michael C. Harris, Jeffrey H. Gruger, Alan D. Gant, Harold D. Shelton, James R. Weatherford, Arthur T. Kimmel, Gary B. Gostin, Gilbert J. Hansen, John M. Golenbieski, Larry W. Spry, Gerald Matulka, Gaynel J. Lockhart, Michael E. Sydow