Abstract: Methods, devices, and systems for accessing packed registers are presented. A state of the packed registers may be tracked and it may be determined whether the register is directly accessible based on the state. If the register is not directly accessible, an action may be performed which allows the register to be accessed directly. The action may include injecting at least one uop for reorganizing the physical storage of the register such that it is directly accessible. The action may include aligning the data with the least significant bit of a physical register or otherwise aligning the data with the datapath. The action may also include changing the state of the packed registers.

Abstract: Method and apparatus for implementing a plurality of RDR chains, wherein each of the RDR chains comprises at least one RDR is described. In one embodiment, the method comprises, responsive to execution of a first instruction identifying one of the RDR chains and one of the RDRs of the identified RDR chain, reading data from the identified RDR of the identified RDR chain and, responsive to issuance of a second instruction identifying one of the RDR chains and one of the RDRs of the identified RDR chain, writing data to the identified RDR of the identified RDR chain.

Abstract: A method and apparatus for implementing a semaphore on a multi-core processor including a central arbitration unit (CAU) connected to each core thereof. The scheme involves, for each core, outputting a first signal from the core to the CAU to request access to a common resource to perform an operation; and responsive to receipt of a second signal from the CAU, the core performing the operation.

Abstract: Method and apparatus for implementing a plurality of RDR chains, wherein each of the RDR chains comprises at least one RDR is described. In one embodiment, the method comprises, responsive to execution of a first instruction identifying one of the RDR chains and one of the RDRs of the identified RDR chain, reading data from the identified RDR of the identified RDR chain and, responsive to issuance of a second instruction identifying one of the RDR chains and one of the RDRs of the identified RDR chain, writing data to the identified RDR of the identified RDR chain.

Abstract: An embodiment of the invention provides an improved circuit and method for capturing and observing internal signals on an integrated circuit. Internal signals are routed to a multiplexer that either selects normal-operation signals or debug signals. A counter creates addresses where the debug signals are be stored in an on-chip RAM. A second multiplexer selects either normal-operation addresses or addresses created by the counter. The output of the second multiplexer provides addresses for the on-chip RAM. After debug signals are stored in the on-chip RAM, they may, at a later time, be read from the RAM to a BIST engine.