Abstract: A disk array controller apparatus (10) is disclosed having at least two logical ports (Logical Port #0-Logical Port #3) for interfacing with a host (12) and having one or more physical ports (Physical Port #0-Physical Port #4), each physical port arranged for attaching at least one disk drive to the controller, and the controller including a switch (26), the switch providing dynamically configurable data paths (30) between the logical data ports and physical data ports, responsive to the contents of a Mapping Register (24). The Mapping Register defines a desired disk drive array by specifying an association of each logical port to one of the physical ports. The mapping register can be organized as a logical mapping register, comprising a field for each logical port of the controller, and includes provision for designating a redundant array for RAID operations.

Abstract: A RAID disk drive controller (FIG. 33) implements disk storage operations, including striping and redundancy operations with multiple disk drives connected via respective SATA ports (520). Configurable data path switch logic (460) provides dynamic configuration of two or more attached drives into one or more arrays. Data transfers are synchronized locally by leveraging the SATA port transport layer FIFO (530). Synchronous transfers allow on-the-fly redundancy (XOR) operations (FIG. 36) for improved performance and reduced hardware complexity. XOR accumulator hardware (FIG. 42-FIG. 43) reduces buffer requirements for multiple DMA channels otherwise required for synchronization, and various narrow and wide striping modes are supported.

Abstract: A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g., level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Abstract: A RAID disk drive controller (FIG. 33) implements disk storage operations, including striping and redundancy operations with multiple disk drives connected via respective SATA ports (520). Configurable data path switch logic (460) provides dynamic configuration of two or more attached drives into one or more arrays. Data transfers are synchronized locally by leveraging the SATA port transport layer FIFO (530). Synchronous transfers allow on-the-fly redundancy (XOR) operations (FIG. 36) for improved performance and reduced hardware complexity. XOR accumulator hardware (FIG. 42-FIG. 43) reduces buffer requirements for multiple DMA channels otherwise required for synchronization, and various narrow and wide striping modes are supported.

Abstract: A RAID disk drive controller (FIG. 33) implements disk storage operations, including striping and redundancy operations with multiple disk drives connected via respective SATA ports (520). Configurable data path switch logic (460) provides dynamic configuration of two or more attached drives into one or more arrays. Data transfers are synchronized locally by leveraging the SATA port transport layer FIFO (530). Synchronous transfers allow on-the-fly redundancy (XOR) operations (FIG. 36) for improved performance and reduced hardware complexity. XOR accumulator hardware (FIG. 42-FIG. 43) reduces buffer requirements for multiple DMA channels otherwise required for synchronization, and various narrow and wide striping modes are supported.

Abstract: A RAID disk drive controller (FIG. 33) implements disk storage operations, including striping and redundancy operations with multiple disk drives connected via respective SATA ports (520). Configurable data path switch logic (460) provides dynamic configuration of two or more attached drives into one or more arrays. Data transfers are synchronized locally by leveraging the SATA port transport layer FIFO (530). Synchronous transfers allow on-the-fly redundancy (XOR) operations (FIG. 36) for improved performance and reduced hardware complexity. XOR accumulator hardware (FIG. 42-FIG. 43) reduces buffer requirements for multiple DMA channels otherwise required for synchronization, and various narrow and wide striping modes are supported.

Abstract: A RAID disk drive controller (FIG. 33) implements disk storage operations, including striping and redundancy operations with multiple disk drives connected via respective SATA ports (520). Configurable data path switch logic (460) provides dynamic configuration of two or more attached drives into one or more arrays. Data transfers are synchronized locally by leveraging the SATA port transport layer FIFO (530). Synchronous transfers allow on-the-fly redundancy (XOR) operations (FIG. 36) for improved performance and reduced hardware complexity. XOR accumulator hardware (FIG. 42-FIG. 43) reduces buffer requirements for multiple DMA channels otherwise required for synchronization, and various narrow and wide striping modes are supported.

Abstract: The present disclosure pertains to multiple-platter disk drive digital data storage with integrated redundancy operations for improved reliability. Within a single disk drive assembly (300), one or more individual storage platters (304) can be used to store redundant data, enabling recovery of user data in the event that another platter (302) is defective, fails or is otherwise unavailable. “On-the-fly” redundancy operations (FIGS. 6A,6B) can be made transparent to the user or host, and impose no significant speed penalty. A data path switch (26) can reconfigure mappings between logical ports and platter interfaces (210) as needed.

Abstract: A RAID disk array controller implements a write mask to support partial-stripe updates from a host system without expensive RAM to RAM copying and repeated disk accesses to assemble the updated stripe. New data from the host is transferred into a single buffer and a local processor tracks—by setting bits in the write mask—which segments of the target stripe are updated. The disk array is accessed to transfer the target stripe into the same buffer, but the buffer memory write enable is inhibited—responsive to the write mask—during transfer of the segments that were updated by the host. The complete, updated stripe is thus formed in a single buffer for parity calculations and write to the disk array.

Abstract: A RAID disk array controller [(FIG. 7)] implements a write mask 16 to support partial-stripe updates [(FIG. 4)] from a host system [60] without expensive RAM to RAM copying and repeated disk accesses to assemble the updated stripe. New data from the host [20,22] is transferred into a single buffer [14,40] and a local processor [80] tracks—by setting bits [30,32] in the write mask—which segments of the target stripe are updated. The disk array is accessed to transfer the target stripe into the same buffer [40], but the buffer memory write enable [58] is inhibited—responsive to the write mask [52]—during transfer of the segments that were updated by the host. The complete, updated stripe is thus formed in a single buffer for parity calculations and write to the disk array.

Abstract: A disk array controller apparatus (10) is disclosed having at least two logical ports (Logical Port #0-Logical Port #3) for interfacing with a host (12) and having one or more physical ports (Physical Port #0-Physical Port #4), each physical port arranged for attaching at least one disk drive to the controller,. and the controller including a switch (26), said switch providing dynamically configurable data paths (30) between the logical data ports and physical data ports, responsive to the contents of a Mapping Register (24). The Mapping Register defines a desired array disk drive array by specifying an association of each logical port to one of the physical ports. The mapping register can be organized as a logical mapping register, comprising a field for each logical port of the controller, and includes provision for designating a redundant array for RAID operations.

Abstract: A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g., level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Abstract: Method and apparatus to effect synchronous data transfers in a disk controller, for example to and from a common buffer (52), when the data transfers to and from the individual disk drives (12,20) are actually asynchronous. A FIFO memory (26,28) is provided in the controller for each disk drive. Asynchronous data transfers between each drive and the corresponding FIFO use the timing provided by the respective drive (interfaces 16,24); whereas data transfers on the buffer side of the FIFOs (46,48) are effected synchronously (44,72). The availability of synchronous data transfers enables “on the fly” generation of redundancy information (FIG. 3) (in the disk write direction) and “on the fly” regeneration of missing data in the read direction (FIG. 4).

Abstract: A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g. level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Abstract: A RAID disk array controller (FIG. 7) implements a write mask 16 to support partial-stripe updates (FIG. 4) from a host system 60 without expensive RAM to RAM copying and repeated disk accesses to assemble the updated stripe. New data from the host 20,22 is transferred into a single buffer 14,40 and a local processor 80 tracks—by setting bits 30,32 in the write mask—which segments of the target stripe are updated. The disk array is accessed to transfer the target stripe into the same buffer 40, but the buffer memory write enable 58 is inhibited—responsive to the write mask 52—during transfer of the segments that were updated by the host. The complete, updated stripe is thus formed in a single buffer for parity calculations and write to the disk array.

Abstract: A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double buffering techniques allows use of a single, common shift clock instead of a series of staggered strobes as required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. “check” or parity data) “on the fly” during a write operation to a RAID array.

Abstract: A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double suffering techniques allows use of a single, common shift clock instead of a series of staggered strobes a required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. "check" or parity date) "on the fly" during a write operation to a RAID array.

Abstract: A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double buffering techniques allows use of a single, common shift clock instead of a series of staggered strobes as required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. “check” or parity data) “on the fly” during a write operation to a RAID array.