Abstract: An interface system between an RDC and a connected resolver dynamically matches an input range of the RDC to the output range of the resolver's output signals. The interface system may include methods and/or apparatuses to determine the amplitude of sinusoidal input signals presented to the RDC by the resolver and to compare the amplitude against high and low threshold values. A gain control signal may be generated, which may be corrected if the detected amplitude either exceeds the high threshold or falls below the low threshold. The gain control signal may be output to a circuit in the RDC or in the resolver that corrects any mismatch that occurs between the RDC input and the resolver output. For example, the gain control signal may control the amplitude of an excitation signal applied to a primary of the resolver or the gain control signal may be applied to an analog to digital converter at the input of the RDC to control its effective input range.

Abstract: Embodiments of the present invention provide a monitoring system that may include a plurality of monitors. Each may have a plurality of input pairs coupled to respective components of a component stack, wherein adjacent monitors each have an input pair coupled to a common component. Embodiments of the present invention provide an integrated circuit that may include a plurality of detectors to locally measure a first group of channels. The integrated circuit may also include a receiver operable to receive a measurement of at least one channel of the first group of channels, and a controller to calculate a correction factor based on the received measurement and a local measurement of the at least one channel and to correct all first group measurements with the correction factor.

Abstract: A method of estimating a change of a variable over a measurement window, including the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.

Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: A method of estimating a change of a variable over a measurement window, comprising the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.

Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Abstract: A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.

Abstract: A successive approximation routine analog-to-digital converter includes a switched-capacitor circuit that samples an input voltage into a plurality of capacitors without the need for power to be dissipated by the analog-to-digital converter. A comparator, coupled to the switched-capacitor circuit, compares a voltage across the capacitors with another voltage during each of a number of iterations. A common mode voltage of the switched-capacitor circuit is boosted during at least some of the iterations. The boost may be accomplished in many different ways and may be different for each of a single-ended, a quasi-differential and fully differential versions of the analog-to-digital converter.

Abstract: A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.

Abstract: A successive approximation routine analog-to-digital converter includes a switched-capacitor circuit that samples an input voltage into a plurality of capacitors without the need for power to be dissipated by the analog-to-digital converter. A comparator, coupled to the switched-capacitor circuit, compares a voltage across the capacitors with another voltage during each of a number of iterations. A common mode voltage of the switched-capacitor circuit is boosted during at least some of the iterations. The boost may be accomplished in many different ways and may be different for each of a single-ended, a quasi-differential and fully differential versions of the analog-to-digital converter.

Abstract: Methods and apparatus for jitter and load insensitive charge transfer are disclosed. A quantity of charge is transferred to or from a load during a transfer interval, wherein the charge transferred is significantly insensitive to load characteristics and variations in the transfer interval. A succession of identical or different quantities of charge may be transferred to or from the load during successive transfer intervals. The charge transfer circuit may be employed in mixed switched/continuous-time circuit configurations, and in particular may be used as a unipolar or bipolar one-bit digital-to-analog converter to provide quantized feedback in a sigma-delta analog-to-digital converter circuit configuration.

Abstract: A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

Abstract: An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.