Patents by Inventor Michael Catherwood
Michael Catherwood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230342158Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to identify a first input instruction in a code stream to be executed, determine that the first input instruction includes an atomic operation designation, and selectively block interrupts for a duration of execution of the first input instruction and a second input instruction. The second input instruction is to immediately follow the first input instruction in the code stream.Type: ApplicationFiled: April 19, 2023Publication date: October 26, 2023Applicant: Microchip Technology IncorporatedInventors: Robert Ellis, Stephen Bowling, Michael Catherwood
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Publication number: 20230176738Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.Type: ApplicationFiled: November 18, 2022Publication date: June 8, 2023Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Ashish Desai
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Publication number: 20230176898Abstract: A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.Type: ApplicationFiled: December 1, 2022Publication date: June 8, 2023Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, Howard Schlunder, David Mickey
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Publication number: 20230176937Abstract: A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.Type: ApplicationFiled: December 6, 2022Publication date: June 8, 2023Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey
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Publication number: 20230176866Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.Type: ApplicationFiled: November 8, 2022Publication date: June 8, 2023Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Ashish Desai, Jason Sachs, Calum Wilkie
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Publication number: 20230176867Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.Type: ApplicationFiled: November 17, 2022Publication date: June 8, 2023Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Ashish Desai, Jason Sachs, Calum Wilkie
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Patent number: 10983931Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.Type: GrantFiled: April 29, 2016Date of Patent: April 20, 2021Assignee: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter
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Patent number: 10802866Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.Type: GrantFiled: April 28, 2016Date of Patent: October 13, 2020Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Michael Catherwood, David Mickey
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Patent number: 10776292Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.Type: GrantFiled: January 17, 2019Date of Patent: September 15, 2020Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter
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Publication number: 20190188163Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.Type: ApplicationFiled: January 17, 2019Publication date: June 20, 2019Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter
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Patent number: 10248521Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.Type: GrantFiled: April 1, 2016Date of Patent: April 2, 2019Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Michael Catherwood, Brant Ivey, Sankar Rangarajan
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Patent number: 10120815Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.Type: GrantFiled: June 16, 2016Date of Patent: November 6, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Michael Catherwood, David Mickey, Bryan Kris
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Publication number: 20160371200Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.Type: ApplicationFiled: June 16, 2016Publication date: December 22, 2016Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Bryan Kris
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Publication number: 20160321075Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.Type: ApplicationFiled: April 28, 2016Publication date: November 3, 2016Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey
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Publication number: 20160321202Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.Type: ApplicationFiled: April 29, 2016Publication date: November 3, 2016Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, David Mickey, Bryan Kris, Calum Wilkie, Jason Sachs, Andreas Reiter
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Publication number: 20160292059Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.Type: ApplicationFiled: April 1, 2016Publication date: October 6, 2016Applicant: Microchip Technology IncorporatedInventors: Michael Catherwood, Brant Ivey, Sankar Rangarajan
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Patent number: 8856406Abstract: A microcontroller includes a central processing unit (CPU); a plurality of peripheral units; and a peripheral trigger generator comprising a user programmable state machine, wherein the peripheral trigger generator is configured to receive a plurality of input signals and is programmable to automate timing functions depending on at least one of said input signals and generate at least one output signal.Type: GrantFiled: September 13, 2012Date of Patent: October 7, 2014Assignee: Microchip Technology IncorporatedInventors: Bryan Kris, Michael Catherwood
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Publication number: 20140075052Abstract: A microcontroller includes a central processing unit (CPU); a plurality of peripheral units; and a peripheral trigger generator comprising a user programmable state machine, wherein the peripheral trigger generator is configured to receive a plurality of input signals and is programmable to automate timing functions depending on at least one of said input signals and generate at least one output signal.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Inventors: Bryan Kris, Michael Catherwood
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Patent number: 8645729Abstract: An integrated circuit device controls power up of an external device used for sensing a process variable independently of whether the integrated circuit device is in a low power sleep mode. Once the external device becomes operational the integrated device, even when still in the low power sleep mode, samples the process variable status of the external device. Low power timing circuits operational during the low power sleep mode control the power up of the external device and sampling of the process variable status thereof. After the sample of the process variable status is taken, the integrated circuit device may be brought out of the low power sleep mode to an operational mode when appropriate as determined from the sampled process variable status.Type: GrantFiled: June 18, 2010Date of Patent: February 4, 2014Assignee: Microchip Technology IncorporatedInventors: Michael Simmons, Michael Catherwood
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Publication number: 20110179297Abstract: An integrated circuit device controls power up of an external device used for sensing a process variable independently of whether the integrated circuit device is in a low power sleep mode. Once the external device becomes operational the integrated device, even when still in the low power sleep mode, samples the process variable status of the external device. Low power timing circuits operational during the low power sleep mode control the power up of the external device and sampling of the process variable status thereof. After the sample of the process variable status is taken, the integrated circuit device may be brought out of the low power sleep mode to an operational mode when appropriate as determined from the sampled process variable status.Type: ApplicationFiled: June 18, 2010Publication date: July 21, 2011Inventors: Michael Simmons, Michael Catherwood