Patents by Inventor Michael Chaine
Michael Chaine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901727Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: GrantFiled: November 12, 2021Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: James Davis, Michael Chaine
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Publication number: 20220069572Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: ApplicationFiled: November 12, 2021Publication date: March 3, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: James Davis, Michael Chaine
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Patent number: 11183837Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: GrantFiled: December 18, 2018Date of Patent: November 23, 2021Assignee: Micron Technology, Inc.Inventors: James Davis, Michael Chaine
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Publication number: 20190148934Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: ApplicationFiled: December 18, 2018Publication date: May 16, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: James Davis, Michael Chaine
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Patent number: 10193334Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: GrantFiled: February 22, 2016Date of Patent: January 29, 2019Assignee: Micron Technology, Inc.Inventors: James Davis, Michael Chaine
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Patent number: 9705318Abstract: Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.Type: GrantFiled: April 7, 2014Date of Patent: July 11, 2017Assignee: Micron Techology, Inc.Inventors: Michael Chaine, Xiaofeng Fan
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Patent number: 9607930Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: May 2, 2016Date of Patent: March 28, 2017Assignee: Micron Technologies, Inc.Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 9490631Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.Type: GrantFiled: May 12, 2014Date of Patent: November 8, 2016Assignee: Micron Technology, Inc.Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
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Publication number: 20160247747Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Publication number: 20160172847Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor, The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Applicant: Micron Technology, Inc.Inventors: James Davis, Michael Chaine
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Patent number: 9343368Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: July 7, 2014Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 9281682Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: GrantFiled: March 12, 2013Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: James Davis, Michael Chaine
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Publication number: 20140319697Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: ApplicationFiled: July 7, 2014Publication date: October 30, 2014Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Publication number: 20140268438Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: Micron Technology, Inc.Inventors: James Davis, Michael Chaine
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Publication number: 20140240883Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.Type: ApplicationFiled: May 12, 2014Publication date: August 28, 2014Applicant: Micron Technology, Inc.Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
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Publication number: 20140218830Abstract: Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: Micron Technology, Inc.Inventors: Michael Chaine, Xiaofeng Fan
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Patent number: 8772086Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: March 26, 2013Date of Patent: July 8, 2014Assignee: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Michael Chaine, Kyle K. Kirby, William M. Hiatt
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Patent number: 8724268Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.Type: GrantFiled: August 30, 2011Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventors: Xiaofeng Fan, Michael Chaine, John David Porter
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Patent number: 8693148Abstract: Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.Type: GrantFiled: January 8, 2009Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Michael Chaine, Xiaofeng Fan
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Patent number: 8404521Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.Type: GrantFiled: August 10, 2012Date of Patent: March 26, 2013Assignee: Micron Technology, Inc.Inventors: Michael Chaine, Kyle K. Kirby, William M. Hiatt, Russell D. Slifer