Abstract: A power supply switch for a gallium nitride integrated circuit. The switch includes two or more parallel n-channel transistor switches (FETs). The FETs are controlled by AC gate waveforms of different phases. The use of multiple AC-controlled FETs allows effective DC operation of a bootstrap inverter circuit without requiring a second DC supply voltage.

Abstract: A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.

Abstract: A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

Abstract: The present technology is related to employing a template/macro-based order entry system. An initial order data message contains a macro that establishes the initial parameters for an order and a unique ID is associated with the template. Subsequent, and potentially smaller sized data messages contain the unique ID as well as relevant order details for placing an order. Of course, the technology described herein envisions a much broader concept of reducing message sizes to help improve overall latency and is not limited to order entry.

Abstract: A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Abstract: An antibody-drug conjugate (ADC) comprising an anti-human SEMA4A humanised or human antibody, a linker and a cytotoxin.

Abstract: A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

Abstract: A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.

Abstract: A power supply switch for a gallium nitride integrated circuit. The switch includes two or more parallel n-channel transistor switches (FETs). The FETs are controlled by AC gate waveforms of different phases. The use of multiple AC-controlled FETs allows effective DC operation of a supply switch without requiring a second DC supply voltage.

Abstract: A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.

Abstract: A circuit to enhance the driving capability of conventional inverting bootstrapping GaN drivers. When the inverting driver input is logic high and the driver output is off, the voltage stored on the first bootstrap capacitor for turning on the high side (pull-up) FET of the inverting driver is charged to the full supply voltage using an active charging FET, instead of using a diode or diode-connected FET in a conventional bootstrapping driver. The gate voltage of the active charging FET is bootstrapped to a voltage higher than supply voltage by a second bootstrap capacitor that connects to the inverting driver input, which is at a logic high. The second bootstrap capacitor is charged by an additional diode or diode-connected FET connected to the supply voltage when the inverting driver input is a logic low.

Abstract: The disclosure describes a magnetic induction heating system for viscous and thermally sensitive process streams. The magnetic induction system provides an industrial heating alternative to steam by providing gentle and uniform heating with a high degree of temperature uniformity and stability. The magnetic induction heating system for viscous and thermally sensitive process streams generally includes an induction system that provides gentle heating through a combination of coil design, coupled with a high efficiency heat exchange element capable of gentle heating and through electronic control is such a way unprecedented stability, safety, uniformity, compactness, energy control, and efficiency are achieved.

Abstract: The disclosure describes a magnetic induction heating system for viscous and thermally sensitive process streams. The magnetic induction system provides an industrial heating alternative to steam by providing gentle and uniform heating with a high degree of temperature uniformity and stability. The magnetic induction heating system for viscous and thermally sensitive process streams generally includes an induction system that provides gentle heating through a combination of coil design, coupled with a high efficiency heat exchange element capable of gentle heating and through electronic control is such a way unprecedented stability, safety, uniformity, compactness, energy control, and efficiency are achieved.

Abstract: A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Abstract: An integrated current sensing amplifier with offset cancellation implemented in GaN technology. The current sensing amplifier senses the current flowing through a low side power FET or a high side power FET of a half bridge circuit. The current sensing amplifier uses the off time of the power FET for storing the amplifier input offset voltage. The stored amplifier input offset voltage is then used to cancel the amplifier input offset voltage during the on time of the power FET, which is the interval that requires current sensing.

Abstract: A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

Abstract: A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

Abstract: A circuit to enhance the driving capability of conventional inverting bootstrapping GaN drivers. When the inverting driver input is logic high and the driver output is off, the voltage stored on the first bootstrap capacitor for turning on the high side (pull-up) FET of the inverting driver is charged to the full supply voltage using an active charging FET, instead of using a diode or diode-connected FET in a conventional bootstrapping driver. The gate voltage of the active charging FET is bootstrapped to a voltage higher than supply voltage by a second bootstrap capacitor that connects to the inverting driver input, which is at a logic high. The second bootstrap capacitor is charged by an additional diode or diode-connected FET connected to the supply voltage when the inverting driver input is a logic low.

Abstract: A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.