Abstract: The present description relates generally to methods and systems for an electronic stethoscope device with an active headset, including a speaker to project audio data generated by a chestpiece, the headset defining a closed back volume for the speaker. In this way, the headset provides a back volume of the speakers in order to tune the frequency response of the speakers to a target frequency mimicking the frequency produced by a conventional acoustic stethoscope.

Abstract: A passive radiator and a loudspeaker system are provided. The passive radiator comprises: a radiating surface with geometry providing two surfaces with vertical separation, which are a first surface and a second surface; a primary suspension element, one end of which is connected to the first surface of the radiating surface; and a secondary suspension element, one end of which is connected to the second surface of the radiating surface.

Abstract: A multilayered integrated circuit includes a first layer with a first conductive element overlaying a substrate, a second layer with a second conductive element overlaying the first layer, an intermediate layer between the first layer and the second layer, and a via structure. The via structure is partially embedded within the intermediate layer and is communicatively coupled to the first conductive element and the second conductive element. The via structure extends from the first conductive element and has a first end with a first end width and a second end with a second end width. The second end is further from the substrate than the first end and the first end width is greater than the second end width such that the via structure tapers between the first end and the second end of the via structure.

Abstract: A passive radiator and a loudspeaker system are provided. The passive radiator comprises: a radiating surface with geometry providing two surfaces with vertical separation, which are a first surface and a second surface; a primary suspension element, one end of which is connected to the first surface of the radiating surface; and a secondary suspension element, one end of which is connected to the second surface of the radiating surface.

Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

Abstract: A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.

Abstract: A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer.

Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

Abstract: A computing platform 20 provides multiple computing environments 24 each containing a guest operating system 25 provided by a virtual machine application 26. Optionally, each computing environment 24 is formed in a compartment 220 of a compartmented host operating system 22. A trusted device 213 verifies that the host operating system 22 and each guest operating system 25 operates in a secure and trusted manner by forming integrity metrics which can be interrogated by a user 10. Each computing environment is isolated and secure, and can be verified as trustworthy independent of any other computing environment.

Abstract: Systems, devices and methods are provided for an improved navigational route planning device which provides more understandable, accurate and timely route calculation capabilities. The navigational aid device with route calculation capabilities includes a processor connected to a memory. The memory includes cartographic data and a desired destination, the cartographic data including data indicative of thoroughfares of a plurality of types. A display is connected to the processor and is capable of displaying the cartographic data. The device is adapted to calculate a route to navigate to the desired destination. And, the device is adapted to adjust a starting point for the route calculation to an appropriate location such that the device is on the route at a time when the route calculation is completed. The device processes travel along the route, recognizes when the device has deviated from the route, and calculates a new route to navigate to the desired destination.

Abstract: A method and apparatus are provided for estimating an impedance through a node at an intersection between roads in a roadway network. The impedance may be measured in time or distance, for example. Characteristic information describes at least one feature of the intersecting roads. One or more pieces of characteristic information may impact the impedance of traffic through an intersection and are used to estimate the impedance through the node. Examples of characteristic information are speed information, road-type, network routing level, intersection angle information, one-way, and cross traffic turn information. An impedance factor, or a cost, is assigned to each piece of characteristic information. The cost may be positive if the characteristic information adds impedance to the node, or negative if the characteristic information subtracts impedance from the node.

Abstract: Systems, devices and methods are provided to account for insignificant route segments to enhance a route guidance experience. An electronic navigational aid device is provided according to one aspect. The device includes a processor and a memory adapted to communicate with the processor. The processor and memory are adapted to cooperate to provide route guidance that accounts for insignificant route segments. According to various embodiments, insignificant route segments are accounted for by nullifying and/or modifying route guidance maneuvers associated with the insignificant route segments. Other aspects are provided herein.

Abstract: A method and apparatus are provided for estimating an impedance through a node at an intersection between roads in a roadway network. The impedance may be measured in time or distance, for example. Characteristic information describes at least one feature of the intersecting roads. One or more pieces of characteristic information may impact the impedance of traffic through an intersection and are used to estimate the impedance through the node. Examples of characteristic information are speed information, road-type, network routing level, intersection angle information, one-way, and cross traffic turn information. An impedance factor, or a cost, is assigned to each piece of characteristic information. The cost may be positive if the characteristic information adds impedance to the node, or negative if the characteristic information subtracts impedance from the node.

Abstract: Systems, devices and methods are provided for an improved navigational route planning device which provides more understandable, accurate and timely route calculation capabilities. The navigational aid device with route calculation capabilities includes a processor connected to a memory. The memory includes cartographic data and a desired destination, the cartographic data including data indicative of thoroughfares of a plurality of types. A display is connected to the processor and is capable of displaying the cartographic data. The device is adapted to process the device=s location and travel along a planned route. And, the device is adapted to dynamically calculate a new route to the desired destination with a preference for avoiding a particular portion of a thoroughfare or one or more different thoroughfares in a previous route.

Abstract: Systems, devices and methods are provided for an improved navigational route planning device which provides more understandable, accurate and timely route calculation capabilities. The navigational aid device with route calculation capabilities includes a processor connected to a memory. The memory includes cartographic data and a desired destination, the cartographic data including data indicative of thoroughfares of a plurality of types. A display is connected to the processor and is capable of displaying the cartographic data. The device is adapted to process the device=s location and travel along a planned route. And, the device is adapted to dynamically calculate a new route to the desired destination with a preference for avoiding a particular portion of a thoroughfare or one or more different thoroughfares in a previous route.