Patents by Inventor Michael Child
Michael Child has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11425489Abstract: A passive radiator and a loudspeaker system are provided. The passive radiator comprises: a radiating surface with geometry providing two surfaces with vertical separation, which are a first surface and a second surface; a primary suspension element, one end of which is connected to the first surface of the radiating surface; and a secondary suspension element, one end of which is connected to the second surface of the radiating surface.Type: GrantFiled: June 18, 2020Date of Patent: August 23, 2022Assignee: Goertek Inc.Inventor: Michael Childs
-
Publication number: 20210305152Abstract: A multilayered integrated circuit includes a first layer with a first conductive element overlaying a substrate, a second layer with a second conductive element overlaying the first layer, an intermediate layer between the first layer and the second layer, and a via structure. The via structure is partially embedded within the intermediate layer and is communicatively coupled to the first conductive element and the second conductive element. The via structure extends from the first conductive element and has a first end with a first end width and a second end with a second end width. The second end is further from the substrate than the first end and the first end width is greater than the second end width such that the via structure tapers between the first end and the second end of the via structure.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: DANIEL JAMES DECHENE, Craig Michael Child, Lawrence A. Clevenger, Kisik Choi, Brent Anderson
-
Publication number: 20210006891Abstract: A passive radiator and a loudspeaker system are provided. The passive radiator comprises: a radiating surface with geometry providing two surfaces with vertical separation, which are a first surface and a second surface; a primary suspension element, one end of which is connected to the first surface of the radiating surface; and a secondary suspension element, one end of which is connected to the second surface of the radiating surface.Type: ApplicationFiled: June 18, 2020Publication date: January 7, 2021Applicant: Goertek Inc.Inventor: Michael Childs
-
Patent number: 10593626Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: GrantFiled: October 2, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
-
Patent number: 10340177Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.Type: GrantFiled: February 19, 2016Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ashwini Chandrashekar, Anbu Selvam Km Mahalingam, Craig Michael Child, Jr.
-
Patent number: 10181420Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.Type: GrantFiled: February 6, 2017Date of Patent: January 15, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Jason Eugene Stephens, David Michael Permana, Guillaume Bouche, Andy Wei, Mark Zaleski, Anbu Selvam K M Mahalingam, Craig Michael Child, Jr., Roderick Alan Augur, Shyam Pal, Linus Jang, Xiang Hu, Akshey Sehgal
-
Publication number: 20180226294Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.Type: ApplicationFiled: February 6, 2017Publication date: August 9, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Jason Eugene STEPHENS, David Michael PERMANA, Guillaume BOUCHE, Andy WEI, Mark ZALESKI, Anbu Selvam KM MAHALINGAM, Craig Michael CHILD, JR., Roderick Alan AUGUR, Shyam PAL, Linus JANG, Xiang HU, Akshey SEHGAL
-
Publication number: 20180122744Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: ApplicationFiled: October 2, 2017Publication date: May 3, 2018Inventors: Ruth A. BRAIN, Kevin J. FISCHER, Michael A. CHILDS
-
Patent number: 9818623Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.Type: GrantFiled: March 22, 2016Date of Patent: November 14, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Jason Eugene Stephens, Guillaume Bouche, Byoung Youp Kim, Craig Michael Child, Jr.
-
Patent number: 9812396Abstract: A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.Type: GrantFiled: June 7, 2016Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jason Eugene Stephens, Guillaume Bouche, Shreesh Narasimha, Patrick Ryan Justison, Byoung Youp Kim, Craig Michael Child, Jr.
-
Patent number: 9786545Abstract: A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer.Type: GrantFiled: September 21, 2016Date of Patent: October 10, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Guillaume Bouche, Jason Eugene Stephens, Byoung Youp Kim, Craig Michael Child, Jr., Shreesh Narasimha
-
Patent number: 9780038Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: GrantFiled: October 24, 2016Date of Patent: October 3, 2017Assignee: Intel CorporationInventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
-
Publication number: 20170278720Abstract: A method for forming a pattern for interconnection lines and associated continuity dielectric blocks in an integrated circuit includes providing a structure having a mandrel layer disposed over an etch mask layer, the etch mask layer being disposed over a pattern layer and the pattern layer being disposed over a dielectric stack. Patterning an array of mandrels in the mandrel layer. Selectively etching a beta trench entirely in a mandrel of the array, the beta trench overlaying a beta block mask portion of the pattern layer. Selectively etching a gamma trench entirely in the etch mask layer, the gamma trench overlaying a gamma block mask portion of the pattern layer. Selectively etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.Type: ApplicationFiled: March 22, 2016Publication date: September 28, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Jason Eugene STEPHENS, Guillaume BOUCHE, Byoung Youp KIM, Craig Michael CHILD, JR.
-
Publication number: 20170243783Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Ashwini CHANDRASHEKAR, Anbu Selvam KM MAHALINGAM, Craig Michael CHILD, JR.
-
Patent number: 9627312Abstract: An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.Type: GrantFiled: October 1, 2011Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Michael A. Childs, Kevin J. Fischer, Sanjay S. Natarajan
-
Publication number: 20170040263Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: ApplicationFiled: October 24, 2016Publication date: February 9, 2017Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
-
Patent number: 9502281Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having at least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: GrantFiled: December 29, 2011Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
-
Publication number: 20130320564Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.Type: ApplicationFiled: December 29, 2011Publication date: December 5, 2013Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
-
Publication number: 20130270675Abstract: An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.Type: ApplicationFiled: October 1, 2011Publication date: October 17, 2013Inventors: Michael A. Childs, Kevin J. Fischer, Sanjay S. Natarajan
-
Patent number: 7865876Abstract: A computing platform 20 provides multiple computing environments 24 each containing a guest operating system 25 provided by a virtual machine application 26. Optionally, each computing environment 24 is formed in a compartment 220 of a compartmented host operating system 22. A trusted device 213 verifies that the host operating system 22 and each guest operating system 25 operates in a secure and trusted manner by forming integrity metrics which can be interrogated by a user 10. Each computing environment is isolated and secure, and can be verified as trustworthy independent of any other computing environment.Type: GrantFiled: June 18, 2002Date of Patent: January 4, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jonathan Griffin, Christopher I. Dalton, Michael Child, Liqun Chen, Andrew Patrick Norman