Abstract: A jitter measurement circuit for measuring a jitter of an input signal, the jitter measurement circuit including: a multiplexer configured to output a first comparison signal or a second comparison signal in response to an output signal; a detecting circuit configured to output a detection signal corresponding to a phase difference between an output of the multiplexer and the input signal; a first adder configured to sum the detection signal and a feedback signal; an integrating circuit configured to integrate and output an output of the first adder; a feedback circuit configured to trim an output of the integrating circuit to generate the feedback signal; and a comparator configured to generate an output signal by comparing the output of the integrating circuit with a reference potential.

Abstract: A sample and hold circuit may include: a first transistor connected between a first input terminal configured to receive a first input signal and a first output terminal configured to output a first sampled signal; a second transistor connected between a second input terminal configured to receive a second input signal and a second output terminal configured to output a second sampled signal; a first dummy transistor provided between the first input terminal and the second output terminal; and a second dummy transistor provided between the second input terminal and the first output terminal. A source region and a drain region of the first dummy transistor and a source region and a drain region of the second dummy transistor may not be electrically connected to a metal line connecting the first transistor with the second transistor.

Abstract: An analog-to-digital converter is provided. An analog-to-digital converter comprises an interleaver receiving and processing an input signal that is an analog signal and a plurality of sub-ADCs, wherein the interleaver includes a reference circuit outputting a second voltage based on a first voltage, a high-pass filter receiving the second voltage and outputting a first signal obtained by changing a common mode voltage of the input signal to the second voltage, a sampling circuit generating a second signal obtained by sampling an alternate current component of the first signal, and a buffer outputting a third signal obtained by buffering the second signal by using a buffering circuit, and the sub-ADC converts the third signal into a digital signal by using the first voltage.

Abstract: A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

Abstract: A digital-to-analog converter (DAC) for generating an analog output from a digital input includes a controller configured to generate a control signal based on the digital input, and a segment cell circuit including a plurality of segment cells turned on or off based on the control signal and configured to generate the analog output based on outputs of the plurality of segment cells, wherein the plurality of segment cells include a plurality of first segment cells each configured to generate an output corresponding to each of bits included in a first bit group of the digital input, a plurality of second segment cells each configured to generate an output corresponding to each of bits included in a second bit group of the digital input, and an additional segment cell configured to generate an output corresponding to a lowermost bit among the bits included in the second bit group.

Abstract: A monitoring circuit includes a sensor circuit having a plurality of devices and a selection circuit, which selects a device to be monitored among the plurality of devices, an input circuit, which applies, based on input digital data, a first signal to the device to be monitored and an output circuit, which generates output digital data based on a second signal generated by the sensor circuit. The input circuit includes a digital-to-analog converter, and the output circuit includes an analog-to-digital converter.

Abstract: A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.

Abstract: Provided is an analog-to-digital converter and a voltage offset correction method thereof. The analog-to-digital converter may include a digital-to-analog converter (DAC) configured to generate a first comparison voltage, a comparison circuit configured to output a first comparison result signal based on a result of comparing the first comparison voltage with a second comparison voltage, and a control circuit configured to control the DAC and output an output signal, wherein the DAC may include a correction circuit configured to generate a correction voltage by selectively switching switches connected to terminals to which a plurality of reference voltages are applied, and correct a voltage offset of the comparison circuit based on the correction voltage.

Abstract: An apparatus configured to transmit and receive a radio frequency (RF) signal is provided. The apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal, a power amplifier configured to amplify the analog signal, and an antenna configured to output, as the RF signal, the amplified analog signal to the outside. The DAC includes a current cell matrix including a plurality of current cells configured to generate the analog signal, a plurality of normal paths configured to control the plurality of current cells to be turned on or off, based on the digital signal, and a plurality of alternative paths configured to selectively consume power, based on a pattern of the digital signal.

Abstract: A monitoring circuit includes a sensor circuit having a plurality of devices and a selection circuit, which selects a device to be monitored among the plurality of devices, an input circuit, which applies, based on input digital data, a first signal to the device to be monitored and an output circuit, which generates output digital data based on a second signal generated by the sensor circuit. The input circuit includes a digital-to-analog converter, and the output circuit includes an analog-to-digital converter.

Abstract: An antenna device includes an antenna array including a plurality of first antenna elements, arranged in a 2-by-2 array, a plurality of second antenna elements arranged in a 2-by-2 array, a first switching circuit, a second switching circuit connected to the first switching circuit and the first antenna elements, a third switching circuit connected to the first switching circuit and the second antenna elements, and a processor connected to the switching circuits. The processor is configured to control at least one of the switching circuits to operate in a single mode, among the plurality of modes, based on a single beam pattern among a plurality of predetermined beam patterns and to feed power to the antenna array through the first switching circuit, the second switching circuit, and the third switching circuit, to transmit a signal having the beam pattern.

Abstract: An apparatus configured to transmit and receive a radio frequency (RF) signal is provided. The apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal, a power amplifier configured to amplify the analog signal, and an antenna configured to output, as the RF signal, the amplified analog signal to the outside. The DAC includes a current cell matrix including a plurality of current cells configured to generate the analog signal, a plurality of normal paths configured to control the plurality of current cells to be turned on or off, based on the digital signal, and a plurality of alternative paths configured to selectively consume power, based on a pattern of the digital signal.

Abstract: A digital droop detector for detecting whether a droop occurs in a power supply voltage, may include processing circuitry configured to, detect a voltage level change of a power supply voltage in response to a clock signal, the detecting the voltage level change including converting the detected voltage level change into a first code, correct at least one nonlinearity included in the first code, the correcting including converting the first code into a second code and a target range, and adjust a delay magnitude of the clock signal based on the second code.

Abstract: An analog-to-digital conversion circuit includes analog-to-digital converters (ADCs) including a target analog-to-digital converter (ADC) providing second data samples, a first adjacent ADC providing first data samples, and a second adjacent ADC providing third data samples. The ADCs perform an analog-to-digital conversion using a time-interleaving approach in response to clock signals having different phases and including a reference clock signal. A timing calibration circuit includes a relative time skew generator generating a relative time skew and an absolute time skew generator generate an absolute time skew. A clock generator adjusts at least one phase of the clock signals based on the absolute time skew.

Abstract: A bootstrap circuit for generating an output signal through a pre-charge operation and a sample operation, includes: a sampler including a sampling switch configured to sample an input signal, a first protection switch connected between an input node and the sampling switch, and a second protection switch connected between the sampling switch and an output node; and a driver configured to drive the sampler based on a power supply voltage and the input signal.

Abstract: A multiplexer includes a charging circuit; a plurality of sampling switches receiving a plurality of input signals; and a plurality of boosting circuits connected between the sampling switches and the charging circuit and sharing the charging circuit. First and second charging switches of the charging circuit are controlled by a first clock signal. Each of the boosting circuits includes a first boosting switch connected to a first node of the charging circuit and a gate of one of the sampling switches, a second boosting switch connected between a second node of the charging circuit and the one sampling switch, and a level shifter configured to control the first boosting switch and the second boosting switch in response to a second clock signal and a selection signal.

Abstract: A digital droop detector for detecting whether a droop occurs in a power supply voltage, may include processing circuitry configured to, detect a voltage level change of a power supply voltage in response to a clock signal, the detecting the voltage level change including converting the detected voltage level change into a first code, correct at least one nonlinearity included in the first code, the correcting including converting the first code into a second code and a target range, and adjust a delay magnitude of the clock signal based on the second code.

Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally.

Abstract: A frequency multiplier includes a capacitor circuit having a plurality of capacitors therein, and is responsive to a differential input signal applied to an inverting input node and a non-inverting input node thereof. A frequency multiplication circuit (FMC) is provided, which has a plurality of transistors therein. The FMC is configured to receive components of the differential input signal passing through the plurality of capacitors, and multiply a frequency of the components of the differential input signal. A plurality of inductor loads are provided, which are connected to an inverting output node and a non-inverting output node of the FMC, and are configured to convert a current signal generated by the FMC into a voltage signal.

Abstract: The present invention relates to an innovative thermal design concept of tailoring the absorptance and emittance of a coating—namely silicon oxide (SiOx) coated aluminized Kapton—as a radiator coating for small, nano-satellite (i.e., CubeSat) thermal management. The present invention improves on the thermal design of existing satellites, by: a) thermally coupling all components to the baseplate to eliminate the need for heater power for the battery; b) using all six sides of the CubeSat as radiators by changing the wall material from fiberglass to aluminum; c) using a different ratio of absorptance to emittance for each side by tailoring the SiOx thickness; d) having a high emittance for the wall interior and components; and e) eliminating the need for MLIs. The elimination of the MLIs reduces the volume and increases the clearance to minimize the risk for solar array deployment and cost of the thermal control subsystem.