Abstract: An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

Abstract: A semiconductor device includes a first die manufactured under first process conditions and a second die manufactured under second process conditions. The first die includes a reference generation circuit including a bipolar junction transistor (BJT) element. The second die is configured to operate based on a reference value generated by the reference generation circuit. The first process conditions are different from the second process conditions.

Abstract: A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.

Abstract: Provided is an analog-to-digital converter and a voltage offset correction method thereof. The analog-to-digital converter may include a digital-to-analog converter (DAC) configured to generate a first comparison voltage, a comparison circuit configured to output a first comparison result signal based on a result of comparing the first comparison voltage with a second comparison voltage, and a control circuit configured to control the DAC and output an output signal, wherein the DAC may include a correction circuit configured to generate a correction voltage by selectively switching switches connected to terminals to which a plurality of reference voltages are applied, and correct a voltage offset of the comparison circuit based on the correction voltage.

Abstract: An antenna device includes an antenna array including a plurality of first antenna elements, arranged in a 2-by-2 array, a plurality of second antenna elements arranged in a 2-by-2 array, a first switching circuit, a second switching circuit connected to the first switching circuit and the first antenna elements, a third switching circuit connected to the first switching circuit and the second antenna elements, and a processor connected to the switching circuits. The processor is configured to control at least one of the switching circuits to operate in a single mode, among the plurality of modes, based on a single beam pattern among a plurality of predetermined beam patterns and to feed power to the antenna array through the first switching circuit, the second switching circuit, and the third switching circuit, to transmit a signal having the beam pattern.

Abstract: An attenuator includes: a first transmission line connected between a first terminal and a first node; a second transmission line connected between the first node and a second terminal; a first resistor connected between the first terminal and a ground node; a second resistor connected between the second terminal and the ground node; and a third resistor connected between the first node and the ground node, wherein the first and second resistors each have a resistance that is higher than a resistance of the third resistor.

Abstract: An attenuator includes: a first transmission line connected between a first terminal and a first node; a second transmission line connected between the first node and a second terminal; a first resistor connected between the first terminal and a ground node; a second resistor connected between the second terminal and the ground node; and a third resistor connected between the first node and the ground node, wherein the first and second resistors each have a resistance that is higher than a resistance of the third resistor.

Abstract: A frequency multiplier includes a capacitor circuit having a plurality of capacitors therein, and is responsive to a differential input signal applied to an inverting input node and a non-inverting input node thereof. A frequency multiplication circuit (FMC) is provided, which has a plurality of transistors therein. The FMC is configured to receive components of the differential input signal passing through the plurality of capacitors, and multiply a frequency of the components of the differential input signal. A plurality of inductor loads are provided, which are connected to an inverting output node and a non-inverting output node of the FMC, and are configured to convert a current signal generated by the FMC into a voltage signal.

Abstract: A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

Abstract: An example converter includes a first adder, a first analog-to-digital converter, a second analog-to-digital converter, a digital noise coupling filter, and a digital filter. The first adder is configured to generate a differential analog signal corresponding to a difference between a first analog signal and a second analog signal. The first analog-to-digital converter is configured to convert the differential analog signal to a first digital signal. The second analog-to-digital converter is configured to convert a first quantization error corresponding to a difference between the differential analog signal and the first digital signal to a second digital signal. The digital noise coupling filter is configured to generate a second digital quantization signal corresponding to the second analog signal. The digital filter is configured to generate an output signal based on the first digital signal and the second digital signal.

Abstract: An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

Abstract: A level shifter includes an input circuit configured to invert an input voltage to output a first inverted voltage and a second inverted voltage, wherein the input voltage swings between a first ground voltage and a first power supply voltage, a protection circuit including at least one pair of transistors sharing a gate terminal to adjust, based on the first inverted voltage and the second inverted voltage, one of a first intermediate voltage and a second intermediate voltage of the protection circuit. a cross-coupling circuit configured to adjust the other of the first intermediate voltage and the second intermediate voltage, and an output circuit configured to invert the first intermediate voltage to output an output voltage that swings between a second ground voltage and a second power supply voltage.

Abstract: A digital-to-analog converter (DAC) circuit is provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo random number generation circuit configured to generate random numbers in response to edges of a first clock signal; a first switch circuit connected to a first multiplexer; a second switch circuit connected to a second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively.

Abstract: A jitter measurement circuit for measuring a jitter of an input signal, the jitter measurement circuit including: a multiplexer configured to output a first comparison signal or a second comparison signal in response to an output signal; a detecting circuit configured to output a detection signal corresponding to a phase difference between an output of the multiplexer and the input signal; a first adder configured to sum the detection signal and a feedback signal; an integrating circuit configured to integrate and output an output of the first adder; a feedback circuit configured to trim an output of the integrating circuit to generate the feedback signal; and a comparator configured to generate an output signal by comparing the output of the integrating circuit with a reference potential.

Abstract: A sample and hold circuit may include: a first transistor connected between a first input terminal configured to receive a first input signal and a first output terminal configured to output a first sampled signal; a second transistor connected between a second input terminal configured to receive a second input signal and a second output terminal configured to output a second sampled signal; a first dummy transistor provided between the first input terminal and the second output terminal; and a second dummy transistor provided between the second input terminal and the first output terminal. A source region and a drain region of the first dummy transistor and a source region and a drain region of the second dummy transistor may not be electrically connected to a metal line connecting the first transistor with the second transistor.

Abstract: An analog-to-digital converter is provided. An analog-to-digital converter comprises an interleaver receiving and processing an input signal that is an analog signal and a plurality of sub-ADCs, wherein the interleaver includes a reference circuit outputting a second voltage based on a first voltage, a high-pass filter receiving the second voltage and outputting a first signal obtained by changing a common mode voltage of the input signal to the second voltage, a sampling circuit generating a second signal obtained by sampling an alternate current component of the first signal, and a buffer outputting a third signal obtained by buffering the second signal by using a buffering circuit, and the sub-ADC converts the third signal into a digital signal by using the first voltage.

Abstract: A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

Abstract: A digital-to-analog converter (DAC) for generating an analog output from a digital input includes a controller configured to generate a control signal based on the digital input, and a segment cell circuit including a plurality of segment cells turned on or off based on the control signal and configured to generate the analog output based on outputs of the plurality of segment cells, wherein the plurality of segment cells include a plurality of first segment cells each configured to generate an output corresponding to each of bits included in a first bit group of the digital input, a plurality of second segment cells each configured to generate an output corresponding to each of bits included in a second bit group of the digital input, and an additional segment cell configured to generate an output corresponding to a lowermost bit among the bits included in the second bit group.

Abstract: A monitoring circuit includes a sensor circuit having a plurality of devices and a selection circuit, which selects a device to be monitored among the plurality of devices, an input circuit, which applies, based on input digital data, a first signal to the device to be monitored and an output circuit, which generates output digital data based on a second signal generated by the sensor circuit. The input circuit includes a digital-to-analog converter, and the output circuit includes an analog-to-digital converter.

Abstract: A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.