Abstract: Disclosed is a MEMS device which comprises at least one shape memory material such as a shape memory alloy (SMA) layer and at least one stressed material layer. Examples of such MEMS devices include an actuator, a micropump, a microvalve, or a non-destructive fuse-type connection probe. The device exhibits a variety of improved properties, for example, large deformation ability and high energy density. Also provided is a method of easily fabricating the MEMS device in the form of a cantilever-type or diaphragm-type structure.

Abstract: Disclosed is a MEMS device which comprises at least one shape memory material such as a shape memory alloy (SMA) layer and at least one stressed material layer. Examples of such MEMS devices include an actuator, a micropump, a microvalve, or a non-destructive fuse-type connection probe. The device exhibits a variety of improved properties, for example, large deformation ability and high energy density. Also provided is a method of easily fabricating the MEMS device in the form of a cantilever-type or diaphragm-type structure.

Abstract: A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.

Abstract: A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.

Abstract: A composite wood product manufactured from waney lumber and a method for making the composite wood product. The method utilizes lumber that has been cut from a log such that the piece has a length substantially parallel to the longitudinal axis, a width substantially tangential to the growth rings and a thickness substantially perpendicular to the growth rings. The wane on the lumber is removed to create a complementary side surface for joining in alternating growth ring orientation to the adjoining piece across the joined profiled side surfaces.

Abstract: A microprocessor having a pipelined floating point unit operable to bypass pre-rounded results at clock cycle i and provide the pre-rounded results as an operand for a second instruction at clock cycle i+2. In one embodiment, the pipelined execution unit includes at least a first execution step at clock cycle i, and a second execution step at a clock cycle i+1 and clock cycle i+2. The unit includes a bypass leading from the first execution step at clock cycle i, however, there is no bypass leading from the second execution step at clock cycle i+1. The bypass carries the pre-rounded results from the end of the first execution step to the front end of the pipeline via a latched data path which delays the pre-rounded result one clock cycle.

Abstract: A method and apparatus for calculating a value of a function f(x) for a given operand x. A memory, such as a Read Only Memory, is used to stored precalculated values for some bits of the function f(x) for a plurality of values of the operand x. Bits of the operand x are used to generate bits for the value of the function f(x) in two ways: 1. to address the ROM to generate some bits for the value of f(x), and 2. as inputs to combinational logic to generate an additional bit of the value of f(x). Because one bit of the value for f(x) is generated external to the ROM, the size of the ROM can be reduced without sacrificing accuracy. Alternatively, the ROM can be used to store an additional bit of precision for values of f(x), thereby increasing the accuracy of these values.

Abstract: A control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each command is associated with a route comprising a sequence of route vectors, each identifying an operation to be performed to execute the command, as well as the process, or station, to execute the route vector. In response to the receipt of a command, a control block is generated identifying the first route vector in the route associated with the command. Each station has a work queue containing control blocks, which the station retrieves and processes sequentially. The control block is first sent to the work queue of the station to perform the first operation. When the station gets to the control block, it performs the operation required by the route vector, modifies the control block to identify the next route vector in the sequence, and transfers the control block to the work queue of the station to perform the operation required by the next route vector in the route.