Patents by Inventor Michael Chynoweth
Michael Chynoweth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315453Abstract: An instruction pipeline includes a circuit that can generate a hardware event to indicate conditional branches, including the direction of taken branches. The circuit can generate a forward conditional branch indicator for an opcode when a conditional branch is taken to a forward location from the opcode. The instruction pipeline includes a counter to increment in response to the forward conditional branch indicator, which will indicate a frequency of forward conditional branches for the opcode.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventors: Ahmad YASIN, Lihu RAPPOPORT, Nir TELL, Rami BUSOOL, Eyal HADAS, Michael CHYNOWETH, Joseph OLIVAS, Christopher M. CHRULSKI
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Publication number: 20230305742Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Applicant: Intel CorporationInventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Patent number: 11693588Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: GrantFiled: April 21, 2020Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
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Publication number: 20220308882Abstract: Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.Type: ApplicationFiled: March 27, 2021Publication date: September 29, 2022Inventors: JONATHAN COMBS, MICHAEL CHYNOWETH, BEEMAN STRONG, CHARLIE HEWETT, PATRICK KONSOR, VIDISHA CHIRRA, ASAVARI PARANJAPE, AHMAD YASIN
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Publication number: 20220206819Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Gilles Pokam, Asit Mallick, Martin Dixon, Michael Chynoweth
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Publication number: 20220207154Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Richard Winterton, Mohammad Reza Haghighat, Asit Mallick, Alaa Alameldeen, Abhishek Basak, Jason W. Brandt, Michael Chynoweth, Carlos Rozas, Scott Constable, Martin Dixon, Matthew Fernandez, Fangfei Liu, Francis McKeen, Joseph Nuzman, Gilles Pokam, Thomas Unterluggauer, Xiang Zou
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Patent number: 11093278Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.Type: GrantFiled: June 30, 2017Date of Patent: August 17, 2021Assignee: INTEL CORPORATIONInventors: Michael Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jeremy Shrall
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Publication number: 20200249866Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Patent number: 10649688Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.Type: GrantFiled: November 1, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
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Publication number: 20200142629Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Publication number: 20200125396Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.Type: ApplicationFiled: June 30, 2017Publication date: April 23, 2020Inventors: Michael Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jeremy Shrall