Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block.

Abstract: A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.

Abstract: A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Abstract: This invention relates to a method and system for providing live television and video-on demand content to a plurality of content viewers' devices, the content viewers' devices having a plurality of disparate content viewing applications thereon. A content provider uploads content to a content server and the content server delivers that content in a streaming format upon request to the user devices. In order to upload the content, the content providers access a web page hosted by the content server with a plurality of encoders embedded into the web page. The content providers use the embedded encoders to convert the content into a plurality of streaming formats and upload the content to the content server in the streaming formats. This significantly speeds up the transfer of content to the content server, ensures that the content is made available to the user devices earlier, and obviates the need for additional expensive equipment at the content server.

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Abstract: This invention relates to a method and system for providing live television and video-on demand content to a plurality of content viewers' devices, the content viewers' devices having a plurality of disparate content viewing applications thereon. A content provider uploads content to a content server and the content server delivers that content in a streaming format upon request to the user devices. In order to upload the content, the content providers access a web page hosted by the content server with a plurality of encoders embedded into the web page. The content providers use the embedded encoders to convert the content into a plurality of streaming formats and upload the content to the content server in the streaming formats. This significantly speeds up the transfer of content to the content server, ensures that the content is made available to the user devices earlier, and obviates the need for additional expensive equipment at the content server.

Abstract: A method is provided for the diagnosis of a transmissible spongiform encephalopathy (TSE) or prion disease in an animal which comprises assaying a sample obtained from said animal to determine the number of hematopoietic cells of the erythroid, megakaryocyte or platelet cell lineages in the sample or an expression product thereof.

Abstract: One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second state. A charge storage device is coupled to maintain the node at a first voltage according to an amount of stored charge. A write assist system is connected between the node and a second voltage. The write assist network is configured, when the node is selected, to discharge the charge storage device and to pull the node from the first voltage to a discharge voltage that is outside a range defined by the first voltage and the second voltage to facilitate setting the latch system to another of the first state and the second state.

Abstract: A method for the determination of the sex of an avian subject is provided which comprises analysis of a sample from said subject with a nucleic acid probe comprising an at least 6 base pair fragment from a Female Associated Factor (FAF) nucleic acid sequence, or with an antibody to a protein coded for by said sequences.

Abstract: A method is provided for the diagnosis of a transmissible spongiform encephalopathy (TSE) or prion disease in an animal which comprises assaying a sample obtained from said animal to determine the number of hematopoietic cells of the erythroid, megakaryocyte or platelet cell lineages in the sample or an expression product thereof.

Abstract: A method is provided for the diagnosis of a transmissible spongiform encephalopathy (TSE) or prion disease in an animal which comprises assaying a sample obtained from said animal to determine the number of hematopoietic cells of the erythroid, megakaryocyte or platelet cell lineages in the sample or an expression product thereof.

Abstract: A method is provided for the diagnosis of a transmissible spongiform encephalopathy (TSE) or prion disease in an animal which comprises assaying a sample obtained from said animal to determine the number of hematopoietic cells of the erythroid, megakaryocyte or platelet cell lineages in the sample or an expression product thereof.