Patents by Inventor Michael Collonge

Michael Collonge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7973350
    Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, the piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 5, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Michael Collonge, Maud Vinet
  • Patent number: 7812410
    Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: October 12, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Michael Collonge, Maud Vinet, Olivier Thomas
  • Patent number: 7768821
    Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: August 3, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Olivier Thomas, Michael Collonge, Maud Vinet
  • Publication number: 20090016095
    Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Olivier Thomas, Michael Collonge, Maud Vinet
  • Publication number: 20090014769
    Abstract: A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 15, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Michael Collonge, Maud Vinet, Olivier Thomas
  • Publication number: 20080283877
    Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 20, 2008
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Michael Collonge, Maud Vinet