Abstract: A high-speed modulo exponentiator device employs a computation algorithm and integrated circuit ("IC") hardware implementation to perform the modulo exponentiation function of the form C=B.sup.E (Modulo M) as a series of modulo multiplication operations, which in turn are performed as a series of simple addition, multiplication and distributed modulo operations. The intermediate data maintain a bit length in the range of the bit length of the modulus value. The simplified operations are implemented via register add and shift operations in an arithmetic logic circuit. The arithmetic logic has a bit slice architecture which plural bit slices are combined to form the basic carry-save elements of the exponentiator device. The exponentiator device may be cascaded with other devices for handling numbers of longer bit lengths. Improved techniques are used for optimizing the multiplication time and for pipelining the transfer of data between cascaded elements.