Abstract: A voltage pump comprising a charging transistor responsive to a first control signal, the charging transistor operable to connect a node to a first voltage, a pumping capacitor responsive to a second control signal, the pumping capacitor operable to pump additional charge the node, and a pumping transistor responsive to a third control signal, the pumping transistor operable to connect the node to an output, wherein the charging transistor, the pumping capacitor, and the pumping transistor are thin-gate transistors. A method comprising charging a node to a first voltage, boosting the node to a second voltage, and connecting the node to an output, wherein the absolute value of the gate-to-source, gate-to-drain, and drain-to-source voltages of the plurality of thin-gate transistors does not exceed the absolute value of a supply voltage. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

Abstract: Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that voltages in the circuitry do not exceed predetermined thresholds that, if exceeded, would cause malfunction. In one embodiment of the invention, voltage level translation circuitry is provided to boost voltage from a source voltage (e.g., VCC) to a voltage that is higher in potential (e.g., VCCP) than the source voltage. In another embodiment of the invention, voltage level translation circuitry is provided to pull a ground voltage down to a potential (e.g., VBB) that is lower in voltage than the ground voltage.

Abstract: A voltage pump comprising a charging transistor responsive to a first control signal, the charging transistor operable to connect a node to a first voltage, a pumping capacitor responsive to a second control signal, the pumping capacitor operable to pump additional charge the node, and a pumping transistor responsive to a third control signal, the pumping transistor operable to connect the node to an output, wherein the charging transistor, the pumping capacitor, and the pumping transistor are thin-gate transistors. A method comprising charging a node to a first voltage, boosting the node to a second voltage, and connecting the node to an output, wherein the absolute value of the gate-to-source, gate-to-drain, and drain-to-source voltages of the plurality of thin-gate transistors does not exceed the absolute value of a supply voltage. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes a first one-shot circuit driven by the first transistor. The first one-shot circuit is capable of providing a pulse. The voltage translator also includes a second transistor capable of receiving a complementary signal of the control signal. A first pair and a second pair of transistors are included in the voltage translator. Each pair of transistors is operatively coupled to the first and second transistors. The first and second pairs of transistors are adapted to provide a transition of a signal from a first voltage range to a second voltage range.

Abstract: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

Abstract: Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that voltages in the circuitry do not exceed predetermined thresholds that, if exceeded, would cause malfunction. In one embodiment of the invention, voltage level translation circuitry is provided to boost voltage from a source voltage (e.g., VCC) to a voltage that is higher in potential (e.g., VCCP) than the source voltage. In another embodiment of the invention, voltage level translation circuitry is provided to pull a ground voltage down to a potential (e.g., VBB) that is lower in voltage than the ground voltage.

Abstract: A charge pump includes a pair of capacitors each having a first terminal coupled to a pumped node. A charge voltage is initially applied to the pumped node to charge the capacitors. A second terminal of the first capacitor is then pumped to increase the voltage at the pumped node, with the charge of the first capacitor being shared with the second capacitor. The second terminal of the second capacitor is then pumped to again increase the voltage at the pumped node. The pumped node is then coupled to an output terminal.

Abstract: A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor, and the other electrode of which is connected to a plate line. The bit line is also connected to system ground through a precharge transistor. In a read cycle, the precharge transistor remains on after the word line goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.