Patents by Inventor Michael Cornell
Michael Cornell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946625Abstract: A site light including a body, an arm coupled to the body having an adjustable arm length, a light assembly coupled to the arm opposite the body, and a drive assembly configured to alter the arm length. The drive assembly, in turn, includes a drive wheel mounted for rotation with respect to the body, an idle wheel mounted for rotation with respect to the body, and a biasing member configured to bias the idle wheel toward the drive wheel. The site light also includes a cable coupled to the arm where the cable is positioned between and engaged by both the drive wheel and the idle wheel.Type: GrantFiled: October 30, 2020Date of Patent: April 2, 2024Assignee: MILWAUKEE ELECTRIC TOOL CORPORATIONInventors: David Proeber, Ross McIntyre, Jason D. Thurner, Michael A. Verhagen, Gareth Mueckl, Brian Cornell, Dalton F. Hansen, Anthony R. Sleck, John S. Scott, Scott T. Moeller
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Patent number: 11933481Abstract: A site light including a body, a power system with an AC input and battery terminal, and a telescopic arm assembly supported by the body, where the telescopic arm includes a first end fixed relative to the body and a second end opposite and movable with respect to the first end. The site light also includes a light assembly in operable communication with the power system and coupled to and movable together with the second end of the telescopic arm, where the light assembly is operable in a first light mode in which the light assembly outputs approximately 13,000 lumens of light, and a second light mode in which the light assembly outputs approximately 20,000 lumens of light.Type: GrantFiled: April 27, 2023Date of Patent: March 19, 2024Assignee: Milwaukee Electric Tool CorporationInventors: David Proeber, Ross McIntyre, Jason D. Thurner, Michael A. Verhagen, Gareth Mueckl, Brian Cornell, Dalton F. Hansen, Anthony R. Sleck
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Publication number: 20230415897Abstract: A flexible aircraft privacy door for a passenger cabin environment, comprising a first edge and a second edge. The flexible privacy door is configured to be slidable between a stowed position leaving an opening between spaced structures of an airplane seat and a deployed position closing the opening between the spaced structures of the airplane seat. The first edge of the flexible privacy door, when the flexible privacy door is in the deployed position, is moveable out of a plane of the opening by way of force against the flexible privacy panel. In addition, the flexible privacy door is bendable out of the plane of the airplane seat entrance up to a certain bending distance, thereby allowing a passenger to pass through the opening for ingress/egress during flight operations.Type: ApplicationFiled: January 13, 2023Publication date: December 28, 2023Inventors: Nilesh Dingankar, Spencer Jayoung Lee, Adam Junzo Fukushima, Steven Wesley Conboy, Tyler Stevens Merritt, John Michael Cornell
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Publication number: 20230214939Abstract: Systems and methods for enhanced organizational transparency using a linked activity chain in a ledger are disclosed. In one embodiment, a method may include (1) a back end for an organization comprising at least one computer processor receiving a first communication from a first entity comprising a first customer interaction with the first entity; (2) the back end writing the first communication to a ledger for the organization as a first block in a linked activity chain; (3) the back end receiving a second communication from a second entity comprising a second customer second activity with the second entity; (4) the back end writing the second communication to the ledger for the organization as a second block in the linked activity chain; (5) the back end calculating a summary score for the customer based on the blocks in the linked activity chain.Type: ApplicationFiled: February 24, 2023Publication date: July 6, 2023Inventors: Joe VIEIRA, Kam Sat LEE, Murali PINGALI, Michael CORNELL, Suresh SHETTY, Samer FALAH, Ankur SAMBHAR
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Patent number: 11615482Abstract: Systems and methods for enhanced organizational transparency using a linked activity chain in a ledger are disclosed. In one embodiment, a method may include (1) a back end for an organization comprising at least one computer processor receiving a first communication from a first entity comprising a first customer interaction with the first entity; (2) the back end writing the first communication to a ledger for the organization as a first block in a linked activity chain; (3) the back end receiving a second communication from a second entity comprising a second customer second activity with the second entity; (4) the back end writing the second communication to the ledger for the organization as a second block in the linked activity chain; (5) the back end calculating a summary score for the customer based on the blocks in the linked activity chain.Type: GrantFiled: October 8, 2020Date of Patent: March 28, 2023Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Joe Vieira, Kam Sat Lee, Murali Pingali, Michael Cornell, Suresh Shetty, Samer Falah, Ankur Sambhar
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Publication number: 20210097627Abstract: Systems and methods for enhanced organizational transparency using a linked activity chain in a ledger are disclosed. In one embodiment, a method may include (1) a back end for an organization comprising at least one computer processor receiving a first communication from a first entity comprising a first customer interaction with the first entity; (2) the back end writing the first communication to a ledger for the organization as a first block in a linked activity chain; (3) the back end receiving a second communication from a second entity comprising a second customer second activity with the second entity; (4) the back end writing the second communication to the ledger for the organization as a second block in the linked activity chain; (5) the back end calculating a summary score for the customer based on the blocks in the linked activity chain.Type: ApplicationFiled: October 8, 2020Publication date: April 1, 2021Inventors: Joe VIEIRA, Kam Sat LEE, Murali PINGALI, Michael CORNELL, Suresh SHETTY, Samer FALAH, Ankur SAMBHAR
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Patent number: 10915969Abstract: Systems and methods for enhanced organizational transparency using a linked activity chain in a ledger are disclosed. In one embodiment, a method may include (1) a back end for an organization comprising at least one computer processor receiving a first communication from a first entity comprising a first customer interaction with the first entity; (2) the back end writing the first communication to a ledger for the organization as a first block in a linked activity chain; (3) the back end receiving a second communication from a second entity comprising a second customer second activity with the second entity; (4) the back end writing the second communication to the ledger for the organization as a second block in the linked activity chain; (5) the back end calculating a summary score for the customer based on the blocks in the linked activity chain.Type: GrantFiled: August 11, 2016Date of Patent: February 9, 2021Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Joe Vieira, Kam Sat Lee, Murali Pingali, Michael Cornell, Suresh Shetty, Samer Falah, Ankur Sambhar
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Publication number: 20180047111Abstract: Systems and methods for enhanced organizational transparency using a linked activity chain in a ledger are disclosed. In one embodiment, a method may include (1) a back end for an organization comprising at least one computer processor receiving a first communication from a first entity comprising a first customer interaction with the first entity; (2) the back end writing the first communication to a ledger for the organization as a first block in a linked activity chain; (3) the back end receiving a second communication from a second entity comprising a second customer second activity with the second entity; (4) the back end writing the second communication to the ledger for the organization as a second block in the linked activity chain; (5) the back end calculating a summary score for the customer based on the blocks in the linked activity chain.Type: ApplicationFiled: August 11, 2016Publication date: February 15, 2018Inventors: Joe VIEIRA, Kam Sat LEE, Murali PINGALI, Michael CORNELL, Suresh SHETTY, Samer FALAH, Ankur SAMBHAR
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Patent number: 7850189Abstract: A curb climbing wheelchair system having left and right side attachments are designed to be attached to left and right side portions, respectively, of a standard wheelchair to enable a wheelchair occupant to climb a curb, bump or other obstruction without the aid of another individual. Each attachment includes a ramp extending from a telescoping arm that is designed to be attached, via a clamping system, to one side of the wheelchair. When not in use, the ramps are folded and stowed away on the sides of the wheelchair. During use, the ends of the ramps are placed on the curb to allow the wheelchair occupant to roll up the curb. To retrieve the ramps (now disposed behind the wheelchair), the wheelchair occupant moves the telescoping arms, if necessary with the aid of an attached circular handle, to lift the ramps thus allowing the wheelchair occupant to grab the ramps. The retrieved ramps then are stowed away until needed.Type: GrantFiled: October 16, 2008Date of Patent: December 14, 2010Inventors: Benjamin Barber, Richard Bordoni, Julia Brady, Max Brivic, Michael Cornell, James Doerhoff, Jonathan Goldszmidt, Jeffrey Rovenpor, Sahib Singh, David B. Ponterio, Ahron Rosenfeld
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Publication number: 20090108561Abstract: A curb climbing wheelchair system having left and right side attachments are designed to be attached to left and right side portions, respectively, of a standard wheelchair to enable a wheelchair occupant to climb a curb, bump or other obstruction without the aid of another individual. Each attachment includes a ramp extending from a telescoping arm that is designed to be attached, via a clamping system, to one side of the wheelchair. When not in use, the ramps are folded and stowed away on the sides of the wheelchair. During use, the ends of the ramps are placed on the curb to allow the wheelchair occupant to roll up the curb. To retrieve the ramps (now disposed behind the wheelchair), the wheelchair occupant moves the telescoping arms, if necessary with the aid of an attached circular handle, to lift the ramps thus allowing the wheelchair occupant to grab the ramps. The retrieved ramps then are stowed away until needed.Type: ApplicationFiled: October 16, 2008Publication date: April 30, 2009Inventors: Benjamin Barber, Richard Bordoni, Julia Brady, Max Brivic, Michael Cornell, James Doerhoff, Jonathan Goldszmidt, Jeffrey Rovernpor, Sahib Singh, David B. Ponterio, Ahron Rosenfeld
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Publication number: 20080061375Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: ApplicationFiled: October 30, 2007Publication date: March 13, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard Williams, Michael Cornell, Wai Chen
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Publication number: 20080061376Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: ApplicationFiled: October 30, 2007Publication date: March 13, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20080061377Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: ApplicationFiled: October 30, 2007Publication date: March 13, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20080023762Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: ApplicationFiled: July 30, 2007Publication date: January 31, 2008Applicants: Advanced Analogic Technologies, Inc., Andvanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20070272986Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: ApplicationFiled: July 30, 2007Publication date: November 29, 2007Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Michael Cornell, Wai Chen
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Publication number: 20060246650Abstract: In a trench-gated MOSFET including an epitaxial layer over a substrate of like conductivity and trenches containing thick bottom oxide, sidewall gate oxide, and conductive gates, body regions of the complementary conductivity are shallower than the gates, and clamp regions are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body and clamp regions permits accurate control of dopant concentrations and of junction depth and position. Alternative fabrication processes permit implantation of the body and clamp regions before gate bus formation or through the gate bus after gate bus formation.Type: ApplicationFiled: June 13, 2006Publication date: November 2, 2006Inventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20060223257Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall and which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: ApplicationFiled: April 5, 2006Publication date: October 5, 2006Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong), LimitedInventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20060157818Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: ApplicationFiled: January 29, 2004Publication date: July 20, 2006Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20060014349Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.Type: ApplicationFiled: September 15, 2005Publication date: January 19, 2006Inventors: Richard Williams, Michael Cornell, Wai Chan
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Publication number: 20050272230Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.Type: ApplicationFiled: August 15, 2005Publication date: December 8, 2005Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard Williams, Michael Cornell, Wai Chan