Abstract: Methods of forming, and the intermediate substrate products formed, are disclosed whereby a via is formed in the substrate, followed by a second via. The second via is formed such that it overlap the first via, and may remove a first portion of any via distortion residing within the first via. A third via is then formed in the substrate to at least overlap the first via. The third via may remove a second portion of any via distortion within the first via. The second and third vias are formed on opposite sides of the first via, such that the first, second and third vias together form a symmetrically extended via within the substrate. Optionally, a rigid support film may be provided under the substrate prior to forming the extended via.

Abstract: An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size diameter, the second size diameter being dimensioned larger than the first size diameter, wherein the second via comprises a non-uniform circumference, and wherein the substrate is configured in an approximately 1:1 ratio (i.e., approximately equal number) of the first and second vias. The first and second vias are laser formed or are formed by any of mechanical punching and photolithography. The second via is formed by sequentially forming multiple partially overlapping vias dimensioned and configured with the first size diameter. The first and second vias are arranged in a grid to allow for wiring of electronic devices.

Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.