Abstract: Qubit allocation for noisy intermediate-scale quantum computers is provided. A quantum circuit comprises a plurality of logical qubits. A hardware specification comprising a connectivity graph of a plurality of physical qubits. A directed acyclic allocation graph is determined based on the plurality of logical qubits and the connectivity graph. The allocation graph comprises a node for each possible allocation of the plurality of logical qubits to the plurality of physical qubits, each allocation having a fidelity, and a plurality of directed edges, each edge connecting to its corresponding first node from its corresponding second node, the first node corresponding to a first allocation, the second node corresponding to a sub-allocation of the first allocation. The allocation graph is searched for a weighted shortest path from a root node of the allocation graph to a leaf node of the allocation graph. The allocation corresponding to the weighted shortest path is outputted.

Abstract: Qubit allocation for noisy intermediate-scale quantum computers is provided. In various embodiments, a description of a quantum circuit is received. The quantum circuit comprises a plurality of logical qubits. A hardware specification is received. The hardware specification comprises a connectivity graph of a plurality of physical qubits. A directed acyclic allocation graph is determined based on the plurality of logical qubits and the connectivity graph. The allocation graph comprises a node for each possible allocation of the plurality of logical qubits to the plurality of physical qubits, each allocation having a fidelity, and a plurality of directed edges, each edge connecting to its corresponding first node from its corresponding second node, the first node corresponding to a first allocation, the second node corresponding to a sub-allocation of the first allocation.