Abstract: Method, computer program product, and system for reserving space for standard cells in a circuit layout. A matrix is formed from a pool of standard cells that connect to ports along an edge of a circuit block. The matrix is formed of columns of standard cells, wherein the columns have a length equal to or less than a length of the edge. The number of standard cells that fit in a column depends on dimensions of the standard cells in the direction of the column. The cumulative width of the matrix is equal to the number of columns sufficient to include all of the standard cells in the pool multiplied by the dimension of the standard cells in a direction orthogonal to the direction of the column. The circuit block is placed in the circuit layout such that an area defined by the matrix is reserved for the standard cells.

Abstract: The method includes determining a plurality of metrics for the project, the project having a plurality of subprojects. The method also includes accessing data for each metric from the plurality of metrics, the data concerning a subproject from the plurality of subprojects. The method also includes building a table having the data for a metric matched to the subproject. The method also includes calculating a numerical score based off of the table that represents progress of a first subproject relative to a second subproject with regard to the metric. The method also includes creating a visualization that includes the plurality of metrics and the numerical score of the first subproject.

Abstract: The method includes determining a plurality of metrics for the project, the project having a plurality of subprojects. The method also includes accessing data for each metric from the plurality of metrics, the data concerning a subproject from the plurality of subprojects. The method also includes building a table having the data for a metric matched to the subproject. The method also includes calculating a numerical score based off of the table that represents progress of a first subproject relative to a second subproject with regard to the metric. The method also includes creating a visualization that includes the plurality of metrics and the numerical score of the first subproject.

Abstract: The method includes determining a plurality of metrics for the project, the project having a plurality of subprojects. The method also includes accessing data for each metric from the plurality of metrics, the data concerning a subproject from the plurality of subprojects. The method also includes building a table having the data for a metric matched to the subproject. The method also includes calculating a numerical score based off of the table that represents progress of a first subproject relative to a second subproject with regard to the metric. The method also includes creating a visualization that includes the plurality of metrics and the numerical score of the first subproject.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Abstract: Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: A computer implemented method, system and/or computer program product efficiently manage timing parameters in a circuit. Multiple instances of a definition are implemented onto a circuit. A set of related pins from the multiple instances are defined, and a common assertion value is asserted against all pins in the set of related pins.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: A computer implemented method, system and/or computer program product efficiently manage timing parameters in a circuit. Multiple instances of a definition are implemented onto a circuit. A set of related pins from the multiple instances are defined, and a common assertion value is asserted against all pins in the set of related pins.

Abstract: A system is implemented for controlling long running electronic design automation tools. A user may modify the running of the tool in real time using an interface at the user computer. The user computer accepts user input and communicates with a computer running the design application. The design application runs normally unless a user enters input requiring modification of the process being run by the design application.

Abstract: A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design; measuring a slack difference of each of the plurality of latches; selecting a color for each of the plurality of latches based on the slack difference correspondingly measured for each of the plurality of latches; and generating a graphical image identifying each one of the plurality of latches with slack difference in color, the color selected for each one of the plurality of latches with slack difference being indicative of the severity of the slack difference.

Abstract: A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design; measuring a slack difference of each of the plurality of latches; selecting a color for each of the plurality of latches based on the slack difference correspondingly measured for each of the plurality of latches; and generating a graphical image identifying each one of the plurality of latches with slack difference in color, the color selected for each one of the plurality of latches with slack difference being indicative of the severity of the slack difference.