Abstract: The present invention is a graphics data processor which includes the capability of determining whether a defined pixel location in a graphics display is within a window in an X Y coordinate system. The respective X and Y coordinates of the selected pixel are separately compared with the window limits. The window limits are preferable expressed as the X and Y coordinates of two diagonally opposite vertexes of a rectangular window. The results of this comparison are preferable available in two forms. In a first embodiment a single data processing instruction enables the generation of a digital data word which indicates the relation of the pixel to the window. This digital word includes a separate indication of the relationship of the pixel to the vertical and horizontal window limits. This indication can be used to generate a "trivial rejection" in determining whether a line or line segment passes through the window by ANDing the results for two points on the line.

Abstract: A computer graphics system. The system includes a video memory having a shift register adapted for split shift register transfers, and digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit with a blanking output. Further, logic circuitry enabled by the blanking output is connected to initiate an extra shift clock pulse for the tap point counter during a blanking interval. Other systems, palette devices, and methods are also disclosed.

Abstract: The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

Abstract: A graphics processing system allows for fuller utilization of memory space by allowing freedom in performing X-Y conversions to linear addressing for graphics display. The system takes advantage of the fact that many display pitch dimensions can be defined in terms of powers of 2, thereby allowing for simple shifts in the binary value followed by an addition of two such shifted numbers. For non-even situations full multiplication by the pitch is available. This operation is controlled by the values in two registers, which values in turn control the actual shifting and multiplication functions.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: A palette device for use with a digital computer that produces a video control signal and color code signals for a first bus and where the digital computer has a graphics coprocessor that produces a video control signal and color code signals for a second bus. The palette device includes an input register for holding respective bits from separate sets of input lines including a first set of input lines for signals representing color codes on the first bus and a second set of input lines for signals representing color codes on the second bus. The palette device further has a look-up table memory for supplying color data words in response to color codes from the input register, and a selector circuit connected between the input register and the look-up table memory. The selector circuit is externally controllable to transfer selected color codes from the selected first or second bus to said look-up table memory and to select a video control signal for output depending on the selected bus.

Abstract: The present invention presents a process of moving an array of pixel data representing an image to be displayed from a source memory space to a destination memory space. The array of pixel data is arranged in words containing a plurality of individual pixel datum. The process includes transforming each pixel datum in the word fetched from the source memory space to a colorized pixel datum by individually attaching color information to each pixel datum. The transforming occurs substantially in parallel on all of the pixel data in each word. This technique permits storage of commonly used images such as alphanumeric characters of various fonts or icons in a compressed form with one bit per pixel. These images are formed in color using the color expand operation at the time of drawing into the color display memory. Otherwise these images would need to be stored in multiple bit per pixel color form for all desired colors requiring considerable memory for redundant data.

Abstract: An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.

Abstract: A graphics data processor which includes the capability of determining whether a defined pixel location in a graphics display is within a window in an X Y coordinate system. The respective X and Y coordinates of the selected pixel are separately compared with the window limits. The window limits are preferable expressed as the X and Y coordinates of two diagonally opposite vertexes of a rectangular window. The results of this comparison are preferable available in two forms. In a first embodiment a single data processing instruction enables the generation of a digital data word which indicates the relation of the pixel to the window. This digital word includes a separate indication of the relationship of the pixel to the vertical and horizontal window limits. This indication can be used to generate a "trivial rejection" in determining whether a line or line segment passes through the window by ANDing the results for two points on the line.

Abstract: An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.

Abstract: A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user.

Abstract: The graphics data processing apparatus which can logically combine the color data for two image arrays on a pixel by pixel basis. The logical combination is a nonlinear saturating function. Two examples of such functions are addition with saturation at the maximum value and subtraction with saturation at the minimum value. These functions can be employed to obtain computer graphics effects not feasible using other functions, such as simulating spray painting and light mixing.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

Abstract: A monochrome image becomes expanded into a color image for storage in a bit mapped color display memory. The color expand operation substitutes color data of one of two designated colors for the "1" or "0" monochrome data of a stored monochrome image. The first color code is substituted for all pixels of the monochrome image represented by a "1" and the second color code is substituted for all pixels of the monochrome image represented by a "0". This color expanded image is then stored in the color display memory which controls the color picture shown to the user. This technique permits storage of commonly used images such as alphanumeric characters of various fonts or icons in a compressed form with one bit per pixel. These images are formed in color using the color expand operation at the time of drawing into the color display memory. Otherwise these images would need to be stored in multiple bit per pixel color form for all desired colors requiring considerable memory for redundant data.

Abstract: A graphics data processor which includes the capability of determining whether a defined pixel location in a graphics display is within a window in an X Y coordinate system. The respective X and Y coordinates of the selected pixel are separately compared with the window limits. The window limits are preferable expressed as the X and Y coordinates of two diagonally opposite vertexes of a rectangular window. The results of this comparison are preferably available in two forms. In a first embodiment a single data processing instruction enables the generation of a digital data word which indicates the relation of the pixel to the window. This digital word includes a separate indication of the relationship of the pixel to the vertical and horizontal window limits. This indication can be used to generate a "trivial rejection" in determining whether a line or line segment passes through the window by ANDing the results for two points on the line.

Abstract: The graphics data processing apparatus which can logically combine the color data for two image arrays on a pixel by pixel basis, according to a nonlinear saturating function. Two examples of such functions are addition with saturation at the maximum value and subtraction with saturation at the minimum value. These functions can be employed to obtain computer graphics effects not feasible using other function, such as simulating spray painting and light mixing.

Abstract: The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group.

Abstract: A graphics data processing apparatus having graphic image operations on two images. Two graphic images are formed into a single combined image based upon a predetermined combination of the multibit color codes representing corresponding pixels of the two images. A transparent color code is permitted for the first of the graphic images. The combination of a transparent color code from the first graphic image with any color code from the second graphic image yields the color code of the second graphic image. This innovation enables the use of color codes having selectable numbers of bits set by the number stored in a pixel size register. In particular the transparent color code, which is detected by a transparent color code detection device independent of the image operation, has a selectable number of bits set by the pixel size register in a manner like any other color code.

Abstract: A graphics data processing apparatus having graphic image operations on two images. Two graphic images are formed into a single combined image based upon a predetermined combination of the multibit color codes representing corresponding pixels of the two images. A transparent color code is permitted for the first of the graphic images. The combination of a transparent color code from the first graphic image with any color code from the second graphic image yields the color code of the second graphic image. This innovation enables the use of color codes having selectable numbers of bits set by the number stored in a pixel size register. In particular the transparent color code, which is detected by a transparent color code detection device independent of the image operation, has a selectable number of bits set by the pixel size register in a manner like any other color code.